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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-11-20 11:03:13 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-01 05:49:09 +0100
commit59e03342076ea79cb7c0ed2fdbd199947c8c5212 (patch)
treeec951913b7ad95c35faced30b4dadc6413619b5d /src/mainboard/lippert
parent7d09cfcf749c1c0fd1c3791585065b39ec1a3433 (diff)
downloadcoreboot-59e03342076ea79cb7c0ed2fdbd199947c8c5212.tar.xz
AGESA: Switch to MMCONF_SUPPORT_DEFAULT
Vendorcode always does PCI MMCONF access once it is enabled via MSR. In coreboot proper, we don't give opportunity to make pci_read/write calls before PCI MMCONF is enabled via MSR. This happens early in romstage amd_initmmio() for all cores. Change-Id: If31bc0a67b480bcc1d955632f413f5cdeec51a54 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17533 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/lippert')
-rw-r--r--src/mainboard/lippert/frontrunner-af/romstage.c1
-rw-r--r--src/mainboard/lippert/toucan-af/romstage.c1
2 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c
index ccb6b39bea..37dc37f69f 100644
--- a/src/mainboard/lippert/frontrunner-af/romstage.c
+++ b/src/mainboard/lippert/frontrunner-af/romstage.c
@@ -45,6 +45,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
+ /* Must come first to enable PCI MMCONF. */
amd_initmmio();
if (!cpu_init_detectedx && boot_cpu()) {
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index b2590fc216..adc2987e3d 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -46,6 +46,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
+ /* Must come first to enable PCI MMCONF. */
amd_initmmio();
if (!cpu_init_detectedx && boot_cpu()) {