diff options
| author | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2009-04-21 00:16:06 +0000 |
|---|---|---|
| committer | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2009-04-21 00:16:06 +0000 |
| commit | b5e10bcf1fdaa684189581b65861ab6f7775c4f1 (patch) | |
| tree | 86672cc3153a39c113c2a9e6f6918716d6fda5be /src/mainboard/lippert | |
| parent | 108950972504f37cc354f79a0aa0895eae751523 (diff) | |
| download | coreboot-b5e10bcf1fdaa684189581b65861ab6f7775c4f1.tar.xz | |
Thanks to Myles' patch adding support for include statements,
refactoring Config.lb became possible.
Factor out ROM size calculation from Config.lb.
This patch converts 87 boards (with and without USE_FAILOVER_IMAGE),
but it has to work around a parser bug.
89 files changed, 209 insertions(+), 2415 deletions(-)
A total of 2206 removed lines.
Abuild works for all changed boards on khepri.
Myles writes:
I've tested serengeti for the failover portion and s2892 for the
nofailover portion. ldoptions are exactly the same and they both boot
the same.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/lippert')
| -rw-r--r-- | src/mainboard/lippert/frontrunner/Config.lb | 34 | ||||
| -rw-r--r-- | src/mainboard/lippert/roadrunner-lx/Config.lb | 36 | ||||
| -rw-r--r-- | src/mainboard/lippert/spacerunner-lx/Config.lb | 35 |
3 files changed, 3 insertions, 102 deletions
diff --git a/src/mainboard/lippert/frontrunner/Config.lb b/src/mainboard/lippert/frontrunner/Config.lb index 7dfa0ac556..6859b6a4fa 100644 --- a/src/mainboard/lippert/frontrunner/Config.lb +++ b/src/mainboard/lippert/frontrunner/Config.lb @@ -1,36 +1,4 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end - -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) +include /config/nofailovercalculation.lb ## ## Set all of the defaults for an x86 architecture diff --git a/src/mainboard/lippert/roadrunner-lx/Config.lb b/src/mainboard/lippert/roadrunner-lx/Config.lb index 48436c62a1..d47b5c1897 100644 --- a/src/mainboard/lippert/roadrunner-lx/Config.lb +++ b/src/mainboard/lippert/roadrunner-lx/Config.lb @@ -20,41 +20,7 @@ ## Based on Config.lb from AMD's DB800 and DBM690T mainboards. -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end - -## -## Compute the start location and size size of -## The coreboot bootloader. -## - -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) - +include /config/nofailovercalculation.lb ## ## Set all of the defaults for an x86 architecture diff --git a/src/mainboard/lippert/spacerunner-lx/Config.lb b/src/mainboard/lippert/spacerunner-lx/Config.lb index 8ea92d01e8..98c3b22095 100644 --- a/src/mainboard/lippert/spacerunner-lx/Config.lb +++ b/src/mainboard/lippert/spacerunner-lx/Config.lb @@ -20,40 +20,7 @@ ## Based on Config.lb from AMD's DB800 and DBM690T mainboards. -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) -else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - default ROM_SECTION_OFFSET = 0 -end - -## -## Compute the start location and size size of -## The coreboot bootloader. -## - -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE = 64 * 1024 -default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +include /config/nofailovercalculation.lb ## ## Set all of the defaults for an x86 architecture |