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| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2018-04-17 14:00:34 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-04-27 09:07:43 +0000 |
| commit | 5135f1184df2809e4faeb4ecdcad4bc1cb5af70b (patch) | |
| tree | e6deecf5593037529f32eb5cd418c9aaed7f1b93 /src/mainboard/lowrisc | |
| parent | 062c729c9b7a405c42b020480a1a76f24c5cb868 (diff) | |
| download | coreboot-5135f1184df2809e4faeb4ecdcad4bc1cb5af70b.tar.xz | |
RISC-V boards: Remove PAGETABLES section from memlayout.ld
RISC-V doesn't set up page tables anymore, since commit b26759d703
("arch/riscv: Don't set up virtual memory").
Change-Id: Id1e759b63fb0bc88ab256994d3849d16814affa0
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/lowrisc')
| -rw-r--r-- | src/mainboard/lowrisc/nexys4ddr/memlayout.ld | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/lowrisc/nexys4ddr/memlayout.ld b/src/mainboard/lowrisc/nexys4ddr/memlayout.ld index 0348c47366..86f3667556 100644 --- a/src/mainboard/lowrisc/nexys4ddr/memlayout.ld +++ b/src/mainboard/lowrisc/nexys4ddr/memlayout.ld @@ -26,6 +26,6 @@ SECTIONS STACK(START + 8M, 64K) ROMSTAGE(START + 8M + 64K, 128K) PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) - PAGETABLES(START + 8M + 200K, 56K) + /* hole at (START + 8M + 200K, 56K) */ RAMSTAGE(START + 8M + 256K, 256K) } |