Add support for the Mitac 6513WU mainboard, a Compaq OEM board using the

i810 chipset. Not all hardware has been tested, but my test PC boots Linux
(via FILO) without any problems.

Also: Add support for the SMSC LPC47U33X to the generic 'smscsuperio' driver.

Signed-off-by: Michael Gold <mgold@ncf.ca>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 142 insertions, 0 deletions

diff --git a/src/mainboard/mitac/6513wu/Config.lb b/src/mainboard/mitac/6513wu/Config.lb
new file mode 100644
index 0000000000..5c9a63fe1f
--- /dev/null
+++ b/src/mainboard/mitac/6513wu/Config.lb
@@ -0,0 +1,142 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Michael Gold <mgold@ncf.ca>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
+include /config/nofailovercalculation.lb
+
+arch i386 end
+driver mainboard.o
+if CONFIG_HAVE_PIRQ_TABLE
+	object irq_tables.o
+end
+makerule ./failover.E
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+makerule ./failover.inc
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+makerule ./auto.E
+	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	# Note: The -mcpu=p2 is important, or else... 'too few registers'.
+	action "../romcc -mcpu=p2 -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
+end
+makerule ./auto.inc
+	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	# Note: The -mcpu=p2 is important, or else... 'too few registers'.
+	action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
+end
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+if CONFIG_USE_FALLBACK_IMAGE
+	mainboardinit cpu/x86/16bit/reset16.inc
+	ldscript /cpu/x86/16bit/reset16.lds
+else
+	mainboardinit cpu/x86/32bit/reset32.inc
+	ldscript /cpu/x86/32bit/reset32.lds
+end
+mainboardinit arch/i386/lib/cpu_reset.inc
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+if CONFIG_USE_FALLBACK_IMAGE
+	ldscript /arch/i386/lib/failover.lds
+	mainboardinit ./failover.inc
+end
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+
+dir /pc80
+config chip.h
+
+chip northbridge/intel/i82810           # Northbridge
+  device apic_cluster 0 on              # APIC cluster
+    chip cpu/intel/socket_PGA370        # CPU
+      device apic 0 on end              # APIC
+    end
+  end
+  device pci_domain 0 on                # PCI domain
+    device pci 0.0 on end               # Graphics Memory Controller Hub (GMCH)
+    chip drivers/pci/onboard
+      device pci 1.0 on end
+      register "rom_address" = "0xfff80000" # 512 KB image
+    end
+    chip southbridge/intel/i82801xx     # Southbridge
+      register "pirqa_routing" = "0x03"
+      register "pirqb_routing" = "0x05"
+      register "pirqc_routing" = "0x09"
+      register "pirqd_routing" = "0x0b"
+
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+
+      device pci 1e.0 on                # PCI bridge
+        device pci 5.0 on end           # Audio controller (ESS ES1988)
+      end
+      device pci 1f.0 on                # ISA bridge
+        chip superio/smsc/smscsuperio   # Super I/O (SMSC LPC47U332)
+          device pnp 4e.0 on            # Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 4e.3 on            # Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+            drq 0x74 = 3
+          end
+          device pnp 4e.4 on            # COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 4e.5 on            # MIDI port (MPU-401)
+            io 0x60 = 0x330
+            irq 0x70 = 10
+          end
+          device pnp 4e.7 on            # PS/2 keyboard / mouse
+            io 0x60 = 0x60              # XXX: not relocatable
+            io 0x62 = 0x64              # XXX: not relocatable
+            irq 0x70 = 1                # PS/2 keyboard interrupt
+            irq 0x72 = 12               # PS/2 mouse interrupt
+          end
+          device pnp 4e.9 on            # Game port
+            io 0x60 = 0x201
+          end
+          device pnp 4e.a on            # Runtime registers
+            io 0x60 = 0x400
+          end
+          device pnp 4e.b off end       # SMBus
+        end
+      end
+      device pci 1f.1 on end            # IDE
+      device pci 1f.2 on end            # USB
+      device pci 1f.3 on end            # SMbus
+      device pci 1f.5 off end           # Audio controller
+      device pci 1f.6 off end           # Modem
+    end
+  end
+end