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authorUwe Hermann <uwe@hermann-uwe.de>2009-11-06 17:11:05 +0000
committerMyles Watson <mylesgw@gmail.com>2009-11-06 17:11:05 +0000
commitd63085b20ef40caae1c60a7532b5243e1e30b109 (patch)
treec732b7666d8082775022592eeddedff81375eeef /src/mainboard/mitac/6513wu
parenteeec0ef00a6be64d6846599fe7cf81ead22e2f02 (diff)
downloadcoreboot-d63085b20ef40caae1c60a7532b5243e1e30b109.tar.xz
Drop all pre-CBFS rom_address entries in Config.lb/devicetree.cb.
Since we have CBFS setting rom_address in board files is no longer necessary. Also, drop vga_rom_address from RS690 completely, it was never used in the code. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/mitac/6513wu')
-rw-r--r--src/mainboard/mitac/6513wu/Config.lb1
-rw-r--r--src/mainboard/mitac/6513wu/devicetree.cb1
2 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/mitac/6513wu/Config.lb b/src/mainboard/mitac/6513wu/Config.lb
index c008f99a2b..9072349fc5 100644
--- a/src/mainboard/mitac/6513wu/Config.lb
+++ b/src/mainboard/mitac/6513wu/Config.lb
@@ -82,7 +82,6 @@ chip northbridge/intel/i82810 # Northbridge
device pci 0.0 on end # Graphics Memory Controller Hub (GMCH)
chip drivers/pci/onboard
device pci 1.0 on end
- register "rom_address" = "0xfff80000" # 512 KB image
end
chip southbridge/intel/i82801xx # Southbridge
register "pirqa_routing" = "0x03"
diff --git a/src/mainboard/mitac/6513wu/devicetree.cb b/src/mainboard/mitac/6513wu/devicetree.cb
index 0731b2f2cd..b78dd3aab9 100644
--- a/src/mainboard/mitac/6513wu/devicetree.cb
+++ b/src/mainboard/mitac/6513wu/devicetree.cb
@@ -28,7 +28,6 @@ chip northbridge/intel/i82810 # Northbridge
device pci 0.0 on end # Graphics Memory Controller Hub (GMCH)
chip drivers/pci/onboard
device pci 1.0 on end
- register "rom_address" = "0xfff80000" # 512 KB image
end
chip southbridge/intel/i82801xx # Southbridge
register "pirqa_routing" = "0x03"