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authorUwe Hermann <uwe@hermann-uwe.de>2010-10-13 08:21:44 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-10-13 08:21:44 +0000
commitab50d62ea6867712eca79e9f0770d6ac35f72ce1 (patch)
tree0484728745bb1699e3e4fd2a8f623d508e502661 /src/mainboard/mitac
parent51eafdeae621f1b04db51c3b4a690fa993aa48a0 (diff)
downloadcoreboot-ab50d62ea6867712eca79e9f0770d6ac35f72ce1.tar.xz
Convert all Intel i810 boards to CAR.
- Drop "select ROMCC" from the boards, as well as early_mtrr stuff. - Add "select CACHE_AS_RAM" to socket_PGA370/Kconfig, as well as the usual DCACHE_RAM_BASE and DCACHE_RAM_SIZE variables. - In socket_PGA370/Makefile.inc add: cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc - Other smaller related fixes. Abuild-tested and boot-tested on MSI MS-6178. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/mitac')
-rw-r--r--src/mainboard/mitac/6513wu/Kconfig1
-rw-r--r--src/mainboard/mitac/6513wu/romstage.c20
2 files changed, 4 insertions, 17 deletions
diff --git a/src/mainboard/mitac/6513wu/Kconfig b/src/mainboard/mitac/6513wu/Kconfig
index 77ed6e9153..fac565e97d 100644
--- a/src/mainboard/mitac/6513wu/Kconfig
+++ b/src/mainboard/mitac/6513wu/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_INTEL_I82810
select SOUTHBRIDGE_INTEL_I82801AX
select SUPERIO_SMSC_SMSCSUPERIO
- select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_512
diff --git a/src/mainboard/mitac/6513wu/romstage.c b/src/mainboard/mitac/6513wu/romstage.c
index bbf87568c6..1a2d7c4f0c 100644
--- a/src/mainboard/mitac/6513wu/romstage.c
+++ b/src/mainboard/mitac/6513wu/romstage.c
@@ -26,31 +26,21 @@
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c"
#include "northbridge/intel/i82810/raminit.h"
#include "lib/debug.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
-
-#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
-
-static inline int spd_read_byte(unsigned int device, unsigned int address)
-{
- return smbus_read_byte(device, address);
-}
-
#include "northbridge/intel/i82810/raminit.c"
/* #include "northbridge/intel/i82810/debug.c" */
+#include <lib.h>
-static void main(unsigned long bist)
-{
- if (bist == 0)
- early_mtrr_init();
+#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
+void main(unsigned long bist)
+{
smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
@@ -61,6 +51,4 @@ static void main(unsigned long bist)
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
- /* ram_check(0, 640 * 1024); */
}
-