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| author | Myles Watson <mylesgw@gmail.com> | 2009-11-06 23:42:26 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2009-11-06 23:42:26 +0000 |
| commit | d27c08c2898d1d74765a7799628d1c18369fd671 (patch) | |
| tree | 7ac357d2b44d833c6efe70d1e691c6611c521e8d /src/mainboard/mitac | |
| parent | 547d48ab01049a634dccb16d1847524d5ba93e33 (diff) | |
| download | coreboot-d27c08c2898d1d74765a7799628d1c18369fd671.tar.xz | |
Remove drivers/pci/onboard. The only purpose was for option ROMs, which are
now handled more generically using CBFS.
Simplify the option ROM code in device/pci_rom.c, since there are only two ways
to get a ROM address now (CBFS and the device) and add an exception for qemu.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/mitac')
| -rw-r--r-- | src/mainboard/mitac/6513wu/Config.lb | 4 | ||||
| -rw-r--r-- | src/mainboard/mitac/6513wu/devicetree.cb | 4 |
2 files changed, 2 insertions, 6 deletions
diff --git a/src/mainboard/mitac/6513wu/Config.lb b/src/mainboard/mitac/6513wu/Config.lb index 9072349fc5..a6480bd585 100644 --- a/src/mainboard/mitac/6513wu/Config.lb +++ b/src/mainboard/mitac/6513wu/Config.lb @@ -80,9 +80,7 @@ chip northbridge/intel/i82810 # Northbridge end device pci_domain 0 on # PCI domain device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) - chip drivers/pci/onboard - device pci 1.0 on end - end + device pci 1.0 on end chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x03" register "pirqb_routing" = "0x05" diff --git a/src/mainboard/mitac/6513wu/devicetree.cb b/src/mainboard/mitac/6513wu/devicetree.cb index b78dd3aab9..0369775c07 100644 --- a/src/mainboard/mitac/6513wu/devicetree.cb +++ b/src/mainboard/mitac/6513wu/devicetree.cb @@ -26,9 +26,7 @@ chip northbridge/intel/i82810 # Northbridge end device pci_domain 0 on # PCI domain device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) - chip drivers/pci/onboard - device pci 1.0 on end - end + device pci 1.0 on end chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x03" register "pirqb_routing" = "0x05" |