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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-16 23:15:37 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-16 23:15:37 +0000 |
| commit | 2b6e93bd7ad11e7553e6cd220e1a5038930b09cb (patch) | |
| tree | 9c31d397cfa1da9dd82a1acbae7474bec9db5bf6 /src/mainboard/msi/ms7135/romstage.c | |
| parent | 3226cf8b9cff3dfeda64c189344baa239b375b6e (diff) | |
| download | coreboot-2b6e93bd7ad11e7553e6cd220e1a5038930b09cb.tar.xz | |
Drop W83627THF, it's the same device as W83627THG.
The only difference is that the "G" version is in a Pb-free package, which
is not relevant from a programmer's view.
We keep W83627THG (and drop W83627THF) because:
- The W83627THF had a CIR device / LDN which doesn't actually exist.
- The W83627THF had no GPIO2, GPIO3 LDNs (were commented out).
- The W83627THF didn't use the PNP_MSC0/1 which is needed/used by boards.
This also fixes an issue on MSI MS7135's devicetree.cb:
device pnp 4e.6 off end # XXX keep allocator happy
The line above can be (and is) removed, as it was only needed due to the
incorrect CIR LDN in the W83627THF.
In the iwill/dk8x target: Drop incorrect LDNs 4 and 6, add 0xb.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/msi/ms7135/romstage.c')
| -rw-r--r-- | src/mainboard/msi/ms7135/romstage.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index a4b9cb6567..f6dbb0ae6d 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -22,7 +22,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define SERIAL_DEV PNP_DEV(0x4e, W83627THF_SP1) +#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) #if CONFIG_LOGICAL_CPUS == 1 #define SET_NB_CFG_54 1 @@ -38,7 +38,7 @@ #include <pc80/mc146818rtc.h> #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/winbond/w83627thf/w83627thf_early_serial.c" +#include "superio/winbond/w83627thg/w83627thg_early_serial.c" #include <cpu/amd/model_fxx_rev.h> #include <console/console.h> @@ -123,7 +123,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx); } - w83627thf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); |