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| author | Jonathan Kollasch <jakllsch@kollasch.net> | 2010-10-19 15:17:18 +0000 |
|---|---|---|
| committer | Jonathan A. Kollasch <jakllsch@kollasch.net> | 2010-10-19 15:17:18 +0000 |
| commit | 6f566b7a60a8021399d0603f4a7cfb608e3dfac2 (patch) | |
| tree | 218d0a26daf715ce9bf056b62b2f5af7ac422f11 /src/mainboard/msi/ms7135 | |
| parent | 4e6f4cfa9cb993b92170989cb76786206fa96899 (diff) | |
| download | coreboot-6f566b7a60a8021399d0603f4a7cfb608e3dfac2.tar.xz | |
Use the correct (W83627THF, not W83627HF) superio code in MS-7135 romstage.
This is consistent with the device tree and the chip actually on the board.
Trivial.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5974 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/msi/ms7135')
| -rw-r--r-- | src/mainboard/msi/ms7135/romstage.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 78ac703b65..47da5bca44 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -22,7 +22,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define SERIAL_DEV PNP_DEV(0x4e, W83627HF_SP1) +#define SERIAL_DEV PNP_DEV(0x4e, W83627THF_SP1) /* Used by raminit. */ #define QRANK_DIMM_SUPPORT 1 @@ -41,7 +41,7 @@ #include <pc80/mc146818rtc.h> #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/winbond/w83627hf/w83627hf_early_serial.c" +#include "superio/winbond/w83627thf/w83627thf_early_serial.c" #include <cpu/amd/model_fxx_rev.h> #include <console/console.h> @@ -135,7 +135,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx); } - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627thf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); |