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authorCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2009-04-11 14:51:49 +0000
committerCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2009-04-11 14:51:49 +0000
commitebdc7c7cfebc14d503ab383e1493aa9fd10bd7e8 (patch)
tree9e3992f91a579ceb4aaee2352f5a7654a7bd7b71 /src/mainboard/msi/ms7135
parent4eb37059cea9ad4fae2f959dc023f6537f722717 (diff)
downloadcoreboot-ebdc7c7cfebc14d503ab383e1493aa9fd10bd7e8.tar.xz
Kill remaining unneeded CAR/ROMCC if-blocks.
Lots of Config.lb files still have "if USE_DCACHE_RAM" sections although USE_DCACHE_RAM is always set for them. Such checks are not only pointless, they actively make the files hard to read. A full abuild run confirmed that compilation did not change with this patch applied. The patch does not change whitespace of the remaining code to ease review and svn blame. With this change, it should be possible to have two or three Config.lb variants in total (except the actual hardware config). Right now, some Config.lb have comments, some don't, some have empty lines for better readability, some don't, some have leading whitespace, some don't. This is an utter mess and unifying these files would certainly reduce the headaches I have when looking at them. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/msi/ms7135')
-rw-r--r--src/mainboard/msi/ms7135/Config.lb19
1 files changed, 0 insertions, 19 deletions
diff --git a/src/mainboard/msi/ms7135/Config.lb b/src/mainboard/msi/ms7135/Config.lb
index 1feec7fb63..a0174451cf 100644
--- a/src/mainboard/msi/ms7135/Config.lb
+++ b/src/mainboard/msi/ms7135/Config.lb
@@ -90,7 +90,6 @@ if HAVE_PIRQ_TABLE
object irq_tables.o
end
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
makerule ./auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -104,7 +103,6 @@ if USE_DCACHE_RAM
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
-end
##
## Build our 16 bit and 32 bit coreboot entry code.
@@ -123,12 +121,10 @@ end
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
##
## Build our reset vector (this is where coreboot is entered).
@@ -151,12 +147,6 @@ else
end
end
-if USE_DCACHE_RAM
-else
- ### Should this be in the northbridge code?
- mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
##
## Include an ID string (for safe flashing).
##
@@ -178,13 +168,10 @@ else
end
end
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
-
###
### This is the early phase of coreboot startup.
@@ -193,15 +180,11 @@ end
###
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover_failover.lds
- end
end
else
if USE_FALLBACK_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
- end
end
end
@@ -212,13 +195,11 @@ end
##
## Setup RAM
##
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
-end
##
## Include the secondary configuration files