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authorStefan Reinauer <stepan@coresystems.de>2009-06-30 15:17:49 +0000
committerStefan Reinauer <stepan@openbios.org>2009-06-30 15:17:49 +0000
commit0867062412dd4bfe5a556e5f3fd85ba5b682d79b (patch)
tree81ca5db12b8567b48daaa23a541bfb8a5dc011f8 /src/mainboard/msi/ms7260
parent9702b6bf7ec5a4fb16934f1cf2724480e2460c89 (diff)
downloadcoreboot-0867062412dd4bfe5a556e5f3fd85ba5b682d79b.tar.xz
This patch unifies the use of config options in v2 to all start with CONFIG_
It's basically done with the following script and some manual fixup: VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC` for VAR in $VARS; do find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \; done Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/msi/ms7260')
-rw-r--r--src/mainboard/msi/ms7260/Config.lb46
-rw-r--r--src/mainboard/msi/ms7260/Options.lb216
-rw-r--r--src/mainboard/msi/ms7260/apc_auto.c6
-rw-r--r--src/mainboard/msi/ms7260/cache_as_ram_auto.c24
4 files changed, 146 insertions, 146 deletions
diff --git a/src/mainboard/msi/ms7260/Config.lb b/src/mainboard/msi/ms7260/Config.lb
index fdea44ed0a..d17e0973f2 100644
--- a/src/mainboard/msi/ms7260/Config.lb
+++ b/src/mainboard/msi/ms7260/Config.lb
@@ -18,50 +18,50 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/failovercalculation.lb
arch i386 end
driver mainboard.o
object get_bus_conf.o # Needed by irq_tables and mptable (and acpi_tables).
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
# object reset.o
if CONFIG_USE_INIT
makerule ./cache_as_ram_auto.o
- depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
- action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
end
else
makerule ./cache_as_ram_auto.inc
- depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
- action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
-if USE_FAILOVER_IMAGE
+if CONFIG_USE_FAILOVER_IMAGE
else
if CONFIG_AP_CODE_IN_CAR
makerule ./apc_auto.o
- depends "$(MAINBOARD)/apc_auto.c option_table.h"
- action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
+ action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
end
ldscript /arch/i386/init/ldscript_apc.lb
end
end
-if HAVE_FAILOVER_BOOT
- if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+ if CONFIG_USE_FAILOVER_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
end
else
- if USE_FALLBACK_IMAGE
+ if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
end
@@ -76,8 +76,8 @@ mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/amd/car/cache_as_ram.lds
end
-if HAVE_FAILOVER_BOOT
- if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+ if CONFIG_USE_FAILOVER_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -85,7 +85,7 @@ if HAVE_FAILOVER_BOOT
ldscript /cpu/x86/32bit/reset32.lds
end
else
- if USE_FALLBACK_IMAGE
+ if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -98,13 +98,13 @@ mainboardinit southbridge/nvidia/mcp55/id.inc
ldscript /southbridge/nvidia/mcp55/id.lds
# ROMSTRAP table for MCP55.
-if HAVE_FAILOVER_BOOT
- if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+ if CONFIG_USE_FAILOVER_IMAGE
mainboardinit southbridge/nvidia/mcp55/romstrap.inc
ldscript /southbridge/nvidia/mcp55/romstrap.lds
end
else
- if USE_FALLBACK_IMAGE
+ if CONFIG_USE_FALLBACK_IMAGE
mainboardinit southbridge/nvidia/mcp55/romstrap.inc
ldscript /southbridge/nvidia/mcp55/romstrap.lds
end
@@ -112,12 +112,12 @@ end
mainboardinit cpu/amd/car/cache_as_ram.inc
-if HAVE_FAILOVER_BOOT
- if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+ if CONFIG_USE_FAILOVER_IMAGE
ldscript /arch/i386/lib/failover_failover.lds
end
else
- if USE_FALLBACK_IMAGE
+ if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
end
end
diff --git a/src/mainboard/msi/ms7260/Options.lb b/src/mainboard/msi/ms7260/Options.lb
index b16ebcaf61..9c657d4d0b 100644
--- a/src/mainboard/msi/ms7260/Options.lb
+++ b/src/mainboard/msi/ms7260/Options.lb
@@ -18,137 +18,137 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses USE_FAILOVER_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_FAILOVER_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_USE_FAILOVER_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_FAILOVER_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses CONFIG_MAX_PHYSICAL_CPUS
uses CONFIG_LOGICAL_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses FAILOVER_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_FAILOVER_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION
-uses _RAMBASE
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_RAMBASE
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
-uses HAVE_INIT_TIMER # ?
-uses CROSS_COMPILE
+uses CONFIG_HAVE_INIT_TIMER # ?
+uses CONFIG_CROSS_COMPILE
uses CC
-uses HOSTCC
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses CONFIG_USBDEBUG_DIRECT
-uses HW_MEM_HOLE_SIZEK
-uses HW_MEM_HOLE_SIZE_AUTO_INC
-uses K8_HT_FREQ_1G_SUPPORT
-uses HT_CHAIN_UNITID_BASE
-uses HT_CHAIN_END_UNITID_BASE
-uses SB_HT_CHAIN_ON_BUS0
-uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
-uses DCACHE_RAM_GLOBAL_VAR_SIZE
+uses CONFIG_HW_MEM_HOLE_SIZEK
+uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
+uses CONFIG_K8_HT_FREQ_1G_SUPPORT
+uses CONFIG_HT_CHAIN_UNITID_BASE
+uses CONFIG_HT_CHAIN_END_UNITID_BASE
+uses CONFIG_SB_HT_CHAIN_ON_BUS0
+uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
+uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
uses CONFIG_USE_INIT
-uses SERIAL_CPU_INIT
-uses ENABLE_APIC_EXT_ID
-uses APIC_ID_OFFSET
-uses LIFT_BSP_APIC_ID
+uses CONFIG_SERIAL_CPU_INIT
+uses CONFIG_ENABLE_APIC_EXT_ID
+uses CONFIG_APIC_ID_OFFSET
+uses CONFIG_LIFT_BSP_APIC_ID
uses CONFIG_PCI_64BIT_PREF_MEM
uses CONFIG_LB_MEM_TOPK
uses CONFIG_AP_CODE_IN_CAR
-uses MEM_TRAIN_SEQ
-uses WAIT_BEFORE_CPUS_INIT
+uses CONFIG_MEM_TRAIN_SEQ
+uses CONFIG_WAIT_BEFORE_CPUS_INIT
uses CONFIG_USE_PRINTK_IN_CAR
-default ROM_SIZE = 512 * 1024
-default FALLBACK_SIZE = (256 * 1024) - (4 * 1024)
-default FAILOVER_SIZE = 4 * 1024
+default CONFIG_ROM_SIZE = 512 * 1024
+default CONFIG_FALLBACK_SIZE = (256 * 1024) - (4 * 1024)
+default CONFIG_FAILOVER_SIZE = 4 * 1024
default CONFIG_LB_MEM_TOPK = 2048 # 1MB more for pgtbl.
-default HAVE_FALLBACK_BOOT = 1
-default HAVE_FAILOVER_BOOT = 1
-default HAVE_HARD_RESET = 1
-default HAVE_PIRQ_TABLE = 1
-default IRQ_SLOT_COUNT = 11 # TODO: Check if correct.
-default HAVE_MP_TABLE = 1 # TODO: Check if correct.
-default HAVE_OPTION_TABLE = 1
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_FAILOVER_BOOT = 1
+default CONFIG_HAVE_HARD_RESET = 1
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 11 # TODO: Check if correct.
+default CONFIG_HAVE_MP_TABLE = 1 # TODO: Check if correct.
+default CONFIG_HAVE_OPTION_TABLE = 1
default CONFIG_SMP = 1
default CONFIG_MAX_CPUS = 2
default CONFIG_MAX_PHYSICAL_CPUS = 1
default CONFIG_LOGICAL_CPUS = 1
-# default SERIAL_CPU_INIT = 0
-default ENABLE_APIC_EXT_ID = 0
-default APIC_ID_OFFSET = 0x10
-default LIFT_BSP_APIC_ID = 1
+# default CONFIG_SERIAL_CPU_INIT = 0
+default CONFIG_ENABLE_APIC_EXT_ID = 0
+default CONFIG_APIC_ID_OFFSET = 0x10
+default CONFIG_LIFT_BSP_APIC_ID = 1
# Move the default coreboot CMOS range off of AMD RTC registers.
-default LB_CKS_RANGE_START = 49
-default LB_CKS_RANGE_END = 122
-default LB_CKS_LOC = 123
+default CONFIG_LB_CKS_RANGE_START = 49
+default CONFIG_LB_CKS_RANGE_END = 122
+default CONFIG_LB_CKS_LOC = 123
# Memory hole size. 0 means disable, others will enable the hole. In that
# case, if it is smaller than mmio_basek, it will use mmio_basek instead.
-# default HW_MEM_HOLE_SIZEK = 0x200000 # 2GB
-default HW_MEM_HOLE_SIZEK = 0x100000 # 1GB
-# default HW_MEM_HOLE_SIZEK = 0x80000 # 512MB
+# default CONFIG_HW_MEM_HOLE_SIZEK = 0x200000 # 2GB
+default CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 # 1GB
+# default CONFIG_HW_MEM_HOLE_SIZEK = 0x80000 # 512MB
# Make auto increase hole size to avoid hole_startk equal to basek so as
# to make some kernel happy.
-# default HW_MEM_HOLE_SIZE_AUTO_INC = 1
+# default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC = 1
# Opteron K8 1G HT support.
-default K8_HT_FREQ_1G_SUPPORT = 1
+default CONFIG_K8_HT_FREQ_1G_SUPPORT = 1
# HT Unit ID offset, default is 1, the typical one, 0 means only one HT device.
-default HT_CHAIN_UNITID_BASE = 0
+default CONFIG_HT_CHAIN_UNITID_BASE = 0
# Real SB Unit ID, default is 0x20, mean don't touch it at last.
-# default HT_CHAIN_END_UNITID_BASE = 0x6
+# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
# Make the SB HT chain on bus 0, default is not (0).
-default SB_HT_CHAIN_ON_BUS0 = 2
+default CONFIG_SB_HT_CHAIN_ON_BUS0 = 2
# Only offset for SB chain? Default is yes (1).
-default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
+default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
# Allow capable device use that above 4GB.
# default CONFIG_PCI_64BIT_PREF_MEM = 1
@@ -156,35 +156,35 @@ default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
default CONFIG_CONSOLE_VGA = 1 # Needed for VGA.
default CONFIG_PCI_ROM_RUN = 1 # Needed for VGA.
default CONFIG_USBDEBUG_DIRECT = 0
-default USE_DCACHE_RAM = 1
-default DCACHE_RAM_BASE = 0xc8000
-default DCACHE_RAM_SIZE = 0x08000
-default DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000
+default CONFIG_USE_DCACHE_RAM = 1
+default CONFIG_DCACHE_RAM_BASE = 0xc8000
+default CONFIG_DCACHE_RAM_SIZE = 0x08000
+default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000
default CONFIG_USE_INIT = 0
default CONFIG_AP_CODE_IN_CAR = 0
-default MEM_TRAIN_SEQ = 2
-default WAIT_BEFORE_CPUS_INIT = 0
+default CONFIG_MEM_TRAIN_SEQ = 2
+default CONFIG_WAIT_BEFORE_CPUS_INIT = 0
default CONFIG_IOAPIC = 1
-default MAINBOARD_PART_NUMBER = "K9N Neo (MS-7260)"
-default MAINBOARD_VENDOR = "MSI"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x7260
-default ROM_IMAGE_SIZE = 65536
-default STACK_SIZE = 0x2000
-default HEAP_SIZE = 0x8000
-default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE)
-default _RAMBASE = 0x00100000
+default CONFIG_MAINBOARD_PART_NUMBER = "K9N Neo (MS-7260)"
+default CONFIG_MAINBOARD_VENDOR = "MSI"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x7260
+default CONFIG_ROM_IMAGE_SIZE = 65536
+default CONFIG_STACK_SIZE = 0x2000
+default CONFIG_HEAP_SIZE = 0x8000
+default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE)
+default CONFIG_RAMBASE = 0x00100000
default CONFIG_ROM_PAYLOAD = 1
-default CC = "$(CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
+default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC = "gcc"
default CONFIG_USE_PRINTK_IN_CAR = 1
default CONFIG_CONSOLE_SERIAL8250 = 1
-default TTYS0_BAUD = 115200
-default TTYS0_BASE = 0x3f8
-default TTYS0_LCS = 0x3
-default DEFAULT_CONSOLE_LOGLEVEL = 9
-default MAXIMUM_CONSOLE_LOGLEVEL = 9
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
+default CONFIG_TTYS0_BAUD = 115200
+default CONFIG_TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_LCS = 0x3
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
#
# CBFS
diff --git a/src/mainboard/msi/ms7260/apc_auto.c b/src/mainboard/msi/ms7260/apc_auto.c
index 33217d1d8a..880952b267 100644
--- a/src/mainboard/msi/ms7260/apc_auto.c
+++ b/src/mainboard/msi/ms7260/apc_auto.c
@@ -61,10 +61,10 @@
void hardwaremain(int ret_addr)
{
- struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE -
- DCACHE_RAM_GLOBAL_VAR_SIZE); /* in CACHE */
+ struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE -
+ CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); /* in CACHE */
struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK << 10) -
- DCACHE_RAM_GLOBAL_VAR_SIZE); /* in RAM */
+ CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); /* in RAM */
struct node_core_id id;
id = get_node_core_id_x();
diff --git a/src/mainboard/msi/ms7260/cache_as_ram_auto.c b/src/mainboard/msi/ms7260/cache_as_ram_auto.c
index c9e429d5ca..8089b577e0 100644
--- a/src/mainboard/msi/ms7260/cache_as_ram_auto.c
+++ b/src/mainboard/msi/ms7260/cache_as_ram_auto.c
@@ -43,7 +43,7 @@
/* If we want to wait for core1 done before DQS training, set it to 0. */
#define K8_SET_FIDVID_CORE0_ONLY 1
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -60,7 +60,7 @@
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
-#if USE_FAILOVER_IMAGE == 0
+#if CONFIG_USE_FAILOVER_IMAGE == 0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
@@ -82,7 +82,7 @@
#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
#include "superio/winbond/w83627ehg/w83627ehg_early_init.c"
-#if USE_FAILOVER_IMAGE == 0
+#if CONFIG_USE_FAILOVER_IMAGE == 0
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
@@ -133,7 +133,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#endif
-#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
+#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@@ -194,7 +194,7 @@ normal_image:
);
fallback_image:
-#if HAVE_FAILOVER_BOOT==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1
__asm__ volatile ("jmp __fallback_image":
:"a" (bist), "b"(cpu_init_detectedx)
)
@@ -207,21 +207,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
-#if HAVE_FAILOVER_BOOT == 1
-#if USE_FAILOVER_IMAGE == 1
+#if CONFIG_HAVE_FAILOVER_BOOT == 1
+#if CONFIG_USE_FAILOVER_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#else
real_main(bist, cpu_init_detectedx);
#endif
#else
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
#endif
}
-#if USE_FAILOVER_IMAGE == 0
+#if CONFIG_USE_FAILOVER_IMAGE == 0
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
@@ -235,7 +235,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
};
struct sys_info *sysinfo =
- (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+ (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset = 0;
unsigned bsp_apicid = 0;
@@ -246,7 +246,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
pnp_enter_ext_func_mode(SERIAL_DEV);
/* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */
pnp_write_config(SERIAL_DEV, 0x24, 0);
- w83627ehg_enable_dev(SERIAL_DEV, TTYS0_BASE);
+ w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
pnp_exit_ext_func_mode(SERIAL_DEV);
setup_mb_resource_map();
@@ -268,7 +268,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug_hex8(bsp_apicid);
print_debug("\r\n");
-#if MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ == 1
/* In BSP so could hold all AP until sysinfo is in RAM. */
set_sysinfo_in_ram(0);
#endif