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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-21 17:29:59 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-21 17:29:59 +0000 |
| commit | 57b2ff886e0ce2c92820f5722c8031def3ac94cf (patch) | |
| tree | 3bf95eb33cd3de0b8f2bae495b3ae1453601c4d3 /src/mainboard/msi/ms7260 | |
| parent | 5244e1ba63e5f3ea12066734bfb0d864a8f1f11d (diff) | |
| download | coreboot-57b2ff886e0ce2c92820f5722c8031def3ac94cf.tar.xz | |
Drop excessive whitespace randomly sprinkled in romstage.c files.
Also drop some dead or useless code snippets.
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/msi/ms7260')
| -rw-r--r-- | src/mainboard/msi/ms7260/romstage.c | 11 |
1 files changed, 1 insertions, 10 deletions
diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 7da2361422..329c679dee 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -33,7 +33,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> - #include <console/console.h> #include <usbdebug.h> #include <cpu/amd/model_fxx_rev.h> @@ -43,22 +42,18 @@ #include "lib/delay.c" #include <lib.h> #include <spd.h> - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c" #include "superio/winbond/w83627ehg/w83627ehg_early_init.c" - #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdk8/setup_resource_map.c" +#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" -/* Yes, on the MSI K9N Neo (MS-7260) the Super I/O is at 0x4e! */ #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) -#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" - static void memreset(int controllers, const struct mem_controller *ctrl) {} static inline void activate_spd_rom(const struct mem_controller *ctrl) {} @@ -72,7 +67,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" - #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" @@ -86,11 +80,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -233,4 +225,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* bsp switch stack to RAM and copy sysinfo RAM now. */ post_cache_as_ram(); } - |