Since some people disapprove of white space cleanups mixed in regular commits

while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

4 files changed, 19 insertions, 19 deletions

diff --git a/src/mainboard/msi/ms7260/Kconfig b/src/mainboard/msi/ms7260/Kconfig
index 9752597d7a..cce07a7f94 100644
--- a/src/mainboard/msi/ms7260/Kconfig
+++ b/src/mainboard/msi/ms7260/Kconfig
@@ -15,7 +15,7 @@ config BOARD_MSI_MS7260
 	select LIFT_BSP_APIC_ID
 	select K8_REV_F_SUPPORT
 	select BOARD_ROMSIZE_KB_512
- 
+
 config MAINBOARD_DIR
 	string
 	default msi/ms7260
@@ -25,7 +25,7 @@ config DCACHE_RAM_BASE
 	hex
 	default 0xc8000
 	depends on BOARD_MSI_MS7260
-	
+
 config DCACHE_RAM_SIZE
 	hex
 	default 0x08000
@@ -37,7 +37,7 @@ config DCACHE_RAM_GLOBAL_VAR_SIZE
 	depends on BOARD_MSI_MS7260
 
 config APIC_ID_OFFSET
-	hex	
+	hex
 	default 0x10
 	depends on BOARD_MSI_MS7260
 
@@ -77,7 +77,7 @@ config MAX_PHYSICAL_CPUS
 	depends on BOARD_MSI_MS7260
 
 config HW_MEM_HOLE_SIZE_AUTO_INC
-	bool	
+	bool
 	default n
 	depends on BOARD_MSI_MS7260
 
@@ -87,12 +87,12 @@ config HT_CHAIN_UNITID_BASE
 	depends on BOARD_MSI_MS7260
 
 config HT_CHAIN_END_UNITID_BASE
-	hex	
+	hex
 	default 0x20
 	depends on BOARD_MSI_MS7260
 
 config SERIAL_CPU_INIT
-	bool	
+	bool
 	default n
 	depends on BOARD_MSI_MS7260
 
diff --git a/src/mainboard/msi/ms7260/cmos.layout b/src/mainboard/msi/ms7260/cmos.layout
index 51f4a6c598..5266518e56 100644
--- a/src/mainboard/msi/ms7260/cmos.layout
+++ b/src/mainboard/msi/ms7260/cmos.layout
@@ -1,22 +1,22 @@
-## 
+##
 ## This file is part of the coreboot project.
-## 
+##
 ## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-## 
+##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
 ## the Free Software Foundation; either version 2 of the License, or
 ## (at your option) any later version.
-## 
+##
 ## This program is distributed in the hope that it will be useful,
 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ## GNU General Public License for more details.
-## 
+##
 ## You should have received a copy of the GNU General Public License
 ## along with this program; if not, write to the Free Software
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
+##
 
 # TODO: Check and fix up the values as needed.
 
diff --git a/src/mainboard/msi/ms7260/resourcemap.c b/src/mainboard/msi/ms7260/resourcemap.c
index d72530a3ae..a051500c64 100644
--- a/src/mainboard/msi/ms7260/resourcemap.c
+++ b/src/mainboard/msi/ms7260/resourcemap.c
@@ -163,7 +163,7 @@ static void setup_mb_resource_map(void)
 		 *	   1 = base/limit registers i are read-only
 		 * [ 7: 4] Reserved
 		 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
-		 *	   This field defines the upper address bits of a 40bit address 
+		 *	   This field defines the upper address bits of a 40bit address
 		 *	   that defines the start of memory-mapped I/O region i
 		 */
 		PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
@@ -201,7 +201,7 @@ static void setup_mb_resource_map(void)
 		 * [31:25] Reserved
 		 */
 //		PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
-		PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, 
+		PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
 
@@ -219,7 +219,7 @@ static void setup_mb_resource_map(void)
 		 * [ 3: 2] Reserved
 		 * [ 4: 4] VGA Enable
 		 *	   0 = VGA matches Disabled
-		 *	   1 = matches all address < 64K and where A[9:0] is in the 
+		 *	   1 = matches all address < 64K and where A[9:0] is in the
 		 *	       range 3B0-3BB or 3C0-3DF independen of the base & limit registers
 		 * [ 5: 5] ISA Enable
 		 *	   0 = ISA matches Disabled
@@ -227,7 +227,7 @@ static void setup_mb_resource_map(void)
 		 *	       from matching agains this base/limit pair
 		 * [11: 6] Reserved
 		 * [24:12] PCI I/O Base i
-		 *	   This field defines the start of PCI I/O region n 
+		 *	   This field defines the start of PCI I/O region n
 		 * [31:25] Reserved
 		 */
 //		PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
@@ -272,9 +272,9 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the highest bus number in configuration region i
 		 */
 //		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */
-		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, 
+		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, 
+		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
 
 	};
 
diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 3f7b69dc1b..a5fbffbe4b 100644
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -152,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
 	};
 
-	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE 
+	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
 	int needs_reset = 0;