mainboard: Add MSI MS-7707

* MSI MS-7707 V1.1 (Medion OEM Akoya P4385D MSN10014555)
* SandyBridge Intel P67 (BD82x6x)
* Winbond 25Q32BV (4MB)
* Fintek F71808A
* Intel 82579V Gigabit
* NEC uPD720200 USB 3.0 Host Controller
* IME 7.0.4.1197

Working:
* PCIe gfx adapter
* PS/2 Keyboard
* USB3.0
* Ethernet
* S0/S3/S5
* HWM

Change-Id: I999149bb95d553ed217b2288cc34bce4fe88abb3
Signed-off-by: Max Blau <tripleshiftone@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

1 files changed, 70 insertions, 0 deletions

diff --git a/src/mainboard/msi/ms7707/romstage.c b/src/mainboard/msi/ms7707/romstage.c
new file mode 100644
index 0000000000..30bb545328
--- /dev/null
+++ b/src/mainboard/msi/ms7707/romstage.c
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/pci_ops.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/common/pmbase.h>
+#include <console/console.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void pch_enable_lpc(void)
+{
+	/* IO Decode Ranges Register */
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
+	/* LPC IF Enables Register (CNF2_LPC_EN|KBC_LPC_EN) */
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x2400);
+
+	u16 reg16;
+	reg16 = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xa4);
+	reg16 |= (1 << 13); // WOL Enable Override (WOL_EN_OVRD)
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xa4, reg16);
+}
+
+void mainboard_rcba_config(void)
+{
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{1, 0, 0},
+	{1, 0, 0},
+	{1, 0, 1},
+	{1, 0, 1},
+	{1, 0, 2},
+	{1, 0, 2},
+	{1, 0, 3},
+	{1, 0, 3},
+	{1, 0, 4},
+	{1, 0, 4},
+	{1, 0, 6},
+	{1, 0, 5},
+	{1, 0, 5},
+	{1, 0, 6},
+};
+
+void mainboard_early_init(int s3resume)
+{
+}
+
+void mainboard_config_superio(void)
+{
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+	read_spd(&spd[0], 0x50, id_only);
+	read_spd(&spd[2], 0x52, id_only);
+}