mainboard/ms7721: Add MSI MS-7721 (FM2-A57MA-E35)

Adds support for the MSI MS-7721 (FM2-A75MA-E35) motherboard.

Tested by building coreboot with:
 - VGA bios (needed for onboard video)
 - XHCI firmware
 - SeaBIOS payload

CPU: AMD A8-6500 APU
RAM: 2x 2GB Samsung M378B5673EH1

Confirmed booting using:
 - USB stick with Arch Linux (kernel 4.7.5)
 - Gentoo live CD from SATA dvd drive
 - Gentoo installation from SATA harddisk (kernel 4.4.26)

Change-Id: I757e011de01ca9f340fd524b10e7fa3f291d53e3
Signed-off-by: Renze Nicolai <renze@rnplus.nl>
Reviewed-on: https://review.coreboot.org/17495
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

7 files changed, 216 insertions, 120 deletions

diff --git a/src/mainboard/msi/ms7721/BiosCallOuts.c b/src/mainboard/msi/ms7721/BiosCallOuts.c
index 98bb06781e..09df39baa7 100644
--- a/src/mainboard/msi/ms7721/BiosCallOuts.c
+++ b/src/mainboard/msi/ms7721/BiosCallOuts.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Renze Nicolai <renze@rnplus.nl>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -37,32 +38,31 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
 const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
 
 /**
- * ASUS F2A85-M board ALC887-VD Verb Table
+ * MSI MS-7721 board ALC887-VD Verb Table
  *
- * Copied from `/sys/class/sound/hwC1D0/init_pin_configs` when running
+ * Copied from `/sys/class/sound/hwC1D3/init_pin_configs` when running
  * the vendor BIOS.
  */
-const CODEC_ENTRY f2a85_m_alc887_VerbTbl[] = {
-	{0x11, 0x99430140},
-	{0x12, 0x411111f0},
-	{0x14, 0x01014010},
-	{0x15, 0x01011012},
-	{0x16, 0x01016011},
-	{0x17, 0x01012014},
-	{0x18, 0x01a19850},
-	{0x19, 0x02a19c60},
-	{0x1a, 0x0181305f},
-	{0x1b, 0x02214c20},
-	{0x1c, 0x411111f0},
-	{0x1d, 0x4005e601},
-	{0x1e, 0x01456130},
-	{0x1f, 0x411111f0},
-	{0xff, 0xffffffff}
+const CODEC_ENTRY ms7721_alc887_VerbTbl[] = {
+{0x11, 0x411111f0},
+{0x12, 0x411111f0},
+{0x14, 0x01014410},
+{0x15, 0x01011412},
+{0x16, 0x01016411},
+{0x17, 0x01012414},
+{0x18, 0x01a19c30},
+{0x19, 0x02a19c40},
+{0x1a, 0x0181343f},
+{0x1b, 0x02214c20},
+{0x1c, 0x411111f0},
+{0x1d, 0x4007f603},
+{0x1e, 0x411111f0},
+{0x1f, 0x411111f0}
 };
 
 static const CODEC_TBL_LIST CodecTableList[] =
 {
-	{0x10ec0887, (CODEC_ENTRY*)&f2a85_m_alc887_VerbTbl[0]},
+	{0x10ec0887, (CODEC_ENTRY*)&ms7721_alc887_VerbTbl[0]},
 	{(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
 };
 
diff --git a/src/mainboard/msi/ms7721/Kconfig b/src/mainboard/msi/ms7721/Kconfig
index d520bd493c..7a2623b80b 100644
--- a/src/mainboard/msi/ms7721/Kconfig
+++ b/src/mainboard/msi/ms7721/Kconfig
@@ -3,6 +3,8 @@
 #
 # Copyright (C) 2012 Advanced Micro Devices, Inc.
 # Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
+# Copyright (C) 2016 Renze Nicolai <renze@rnplus.nl>
+
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -25,7 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
 	select HAVE_ACPI_TABLES
-	select SUPERIO_ITE_IT8728F
+	select SUPERIO_FINTEK_F71869AD
 	select BOARD_ROMSIZE_KB_8192
 	select GFXUMA
 	select HUDSON_DISABLE_IMC
@@ -68,11 +70,11 @@ config ONBOARD_VGA_IS_PRIMARY
 
 config VGA_BIOS_ID
 	string
-	default "1002,9993"
+	default "1002,990e"
 
 config HUDSON_LEGACY_FREE
 	bool
-	default y
+	default n
 
 config POST_IO
 	bool
diff --git a/src/mainboard/msi/ms7721/OemCustomize.c b/src/mainboard/msi/ms7721/OemCustomize.c
index a6c9833d72..90bc5a9c13 100644
--- a/src/mainboard/msi/ms7721/OemCustomize.c
+++ b/src/mainboard/msi/ms7721/OemCustomize.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Renze Nicolai <renze@rnplus.nl>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -69,18 +70,30 @@
  */
 
 static const PCIe_PORT_DESCRIPTOR PortList [] = {
-	/* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */
+	/* PCIe port, Lanes 8:23, PCI Device Number 2, x16 slot */
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23),
 		PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
 	},
-	/* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */
+	/* PCIe port, Lane 4, PCI Device Number 4, Realtek LAN */
 	{
 		0,
-		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),
+		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
 		PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
 	},
+	/* PCIe port, Lane 5, PCI Device Number 5, x1 slot (1) */
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
+		PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+	},
+	/* PCIe port, Lane 6, PCI Device Number 6, x1 slot (2) */
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
+		PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+	},
 	/* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */
 	{
 		DESCRIPTOR_TERMINATE_LIST,
@@ -89,12 +102,6 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
 	},
 };
 
-/*
- * It is not known, if the setup is complete.
- *
- * Tested and works: VGA/DVI
- * Untested: HDMI
- */
 static const PCIe_DDI_DESCRIPTOR DdiList [] = {
 	// DP0 to HDMI0/DP
 	{
@@ -205,7 +212,6 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
  *----------------------------------------------------------------------------------------
  */
 
-#if IS_ENABLED(CONFIG_BOARD_MSI_MS7721)
 /*
  *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
  *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
@@ -225,7 +231,6 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
   */
   PSO_END
 };
-#endif /* CONFIG_BOARD_MSI_MS7721 */
 
 const struct OEM_HOOK OemCustomize = {
 	.InitEarly = OemInitEarly,
diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c
index e0a1ea4d3a..ecb168c638 100644
--- a/src/mainboard/msi/ms7721/buildOpts.c
+++ b/src/mainboard/msi/ms7721/buildOpts.c
@@ -326,11 +326,11 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
 #define DFLT_FCH_GPP_PORT3_HOTPLUG          FALSE
 //#define BLDCFG_IR_PIN_CONTROL	0x33
 //#define FCH_NO_XHCI_SUPPORT			FALSE
-GPIO_CONTROL   f2a85_m_gpio[] = {
+GPIO_CONTROL   ms7721_m_gpio[] = {
 //	{183, Function1, PullUpB},
 	{-1}
 };
-#define BLDCFG_FCH_GPIO_CONTROL_LIST           (&f2a85_m_gpio[0])
+#define BLDCFG_FCH_GPIO_CONTROL_LIST           (&ms7721_m_gpio[0])
 
 // The following definitions specify the default values for various parameters in which there are
 // no clearly defined defaults to be used in the common file.  The values below are based on product
diff --git a/src/mainboard/msi/ms7721/devicetree.cb b/src/mainboard/msi/ms7721/devicetree.cb
index 6b728d5ba0..ced99f89e9 100644
--- a/src/mainboard/msi/ms7721/devicetree.cb
+++ b/src/mainboard/msi/ms7721/devicetree.cb
@@ -2,6 +2,7 @@
 # This file is part of the coreboot project.
 #
 # Copyright (C) 2012 Advanced Micro Devices, Inc.
+# Copyright (C) 2016 Renze Nicolai <renze@rnplus.nl>
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -27,25 +28,25 @@ chip northbridge/amd/agesa/family15tn/root_complex
 			chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
 				device pci 0.0 on  end # Root Complex
 				device pci 0.2 on  end # IOMMU
-				device pci 1.0 on  end # Internal Graphics P2P bridge 0x99XX
+				device pci 1.0 on  end # Internal Graphics P2P bridge 0x990e
 				device pci 1.1 on  end # Internal Multimedia
-				device pci 2.0 on  end # PCIE SLOT0 x16 blue
-				device pci 3.0 off end # unused?
-				device pci 4.0 on  end # PCIE 4x black
-				device pci 5.0 off end # unused?
-				device pci 6.0 off end # unused?
+				device pci 2.0 on  end # PCIe x16
+				device pci 3.0 off end # -
+				device pci 4.0 on  end # PCIE Realtek LAN
+				device pci 5.0 on  end # PCIE x1 (1)
+				device pci 6.0 on  end # PCIE x1 (2)
 				device pci 7.0 off end # LAN
 				device pci 8.0 off end # NB/SB Link P2P bridge
 			end	#chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
 
 			chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
-				device pci 10.0 on  end # XHCI HC0
-				device pci 10.1 on  end # XHCI HC1
+				device pci 10.0 on  end # USB XHCI
+				device pci 10.1 on  end # USB XHCI
 				device pci 11.0 on  end # SATA
-				device pci 12.0 on  end # USB
-				device pci 12.2 on  end # USB
-				device pci 13.0 on  end # USB
-				device pci 13.2 on  end # USB
+				device pci 12.0 on  end # USB OHCI
+				device pci 12.2 on  end # USB EHCI
+				device pci 13.0 on  end # USB OHCI
+				device pci 13.2 on  end # USB EHCI
 				device pci 14.0 on      # SMBUS
 					chip drivers/generic/generic #dimm 0
 						device i2c 50 on end # 7-bit SPD address
@@ -55,61 +56,102 @@ chip northbridge/amd/agesa/family15tn/root_complex
 					end
 				end # SM
 				device pci 14.1 off end # IDE	0x439c
-				device pci 14.2 on  end # HDA	0x4383
+				device pci 14.2 on  end # Azalia (Audio)
 				device pci 14.3 on      # LPC	0x439d
-					chip superio/ite/it8728f
-						register hwm_ctl_register = "0xc0"
-						register hwm_main_ctl_register = "0x33"
-						register hwm_adc_temp_chan_en_reg = "0x38"
-						register hwm_fan1_ctl_pwm = "0x00"
-						register hwm_fan2_ctl_pwm = "0x00"
-						register hwm_fan3_ctl_pwm = "0x00"
-
-						device pnp 2e.0 off #  Floppy
-							io 0x60 = 0x3f0
-							irq 0x70 = 6
-							drq 0x74 = 2
-						end
-						device pnp 2e.1 on #  Com1
+					chip superio/fintek/f71869ad
+						register "multi_function_register_1" = "0x01"
+						register "multi_function_register_2" = "0x0f"
+						register "multi_function_register_3" = "0x2f"
+						register "multi_function_register_4" = "0x04"
+						register "multi_function_register_5" = "0x3e"
+
+						# HWM configuration registers
+						register "hwm_smbus_address" = "0x98"
+						register "hwm_smbus_control_reg" = "0x02"
+						register "hwm_fan_type_sel_reg" = "0x00"
+						register "hwm_fan1_temp_adj_rate_reg" = "0x33"
+						register "hwm_fan_mode_sel_reg" = "0x07"
+						register "hwm_fan1_idx_rpm_mode" = "0x0e"
+						register "hwm_fan1_seg1_speed_count" = "0xff"
+						register "hwm_fan1_seg2_speed_count" = "0x0e"
+						register "hwm_fan1_seg3_speed_count" = "0x07"
+						register "hwm_fan1_temp_map_sel" = "0x8c"
+						device pnp 4e.00 off end
+						device pnp 4e.01 on	# COM1
 							io 0x60 = 0x3f8
 							irq 0x70 = 4
 						end
-						device pnp 2e.2 off #  Com2
+						device pnp 4e.02 off	# COM2 (Level converter not populated, but may be usable?)
 							io 0x60 = 0x2f8
 							irq 0x70 = 3
 						end
-						device pnp 2e.3 off #  Parallel Port
+						device pnp 4e.03 on	# Parallel Port
 							io 0x60 = 0x378
-							irq 0x70 = 7
+							irq 0x70 = 5
+							drq 0x74 = 3
+							irq 0xf0 = 0x44 # PRT Mode Select Register
 						end
-						device pnp 2e.4 on #  Env Controller
-							io 0x60 = 0x290
-							io 0x62 = 0x220
+						device pnp 4e.04 on	# Hardware Monitor
+							io 0x60 = 0x600
 							irq 0x70 = 0
 						end
-						device pnp 2e.5 on #  Keyboard
-							io 0x60 = 0x60
-							io 0x62 = 0x64
-							irq 0x70 = 1
-						end
-						device pnp 2e.6 off #  Mouse
-							irq 0x70 = 12
+						device pnp 4e.05 on     # KBC
+							io 0x60 = 0x060
+							irq 0x70 = 1 # Keyboard IRQ
+							irq 0x72 = 12 # Mouse IRQ
 						end
-						device pnp 2e.7 on #  GPIO
-							io 0x60 = 0x228 #SMI
-							io 0x62 = 0x300 #Simple I/O
-							io 0x64 = 0x238 #Phony resource IT8603E does not have it
-							irq 0x70 = 0
-						end
-						device pnp 2e.a off end #  CIR
-					end	#superio/ite/it8728f
+                                                device pnp 4e.06 on     # GPIO
+							# ! GPIO config is disabled because the code in romstage.c
+							# ! has already taken care of it
+                                                        #io 0x60 = 0xa00
+                                                        #irq 0xe0 = 0x04	# GPIO1 output
+                                                        #irq 0xe1 = 0xff	# GPIO1 output data
+                                                        #irq 0xe3 = 0x04	# GPIO1 drive enable
+                                                        #irq 0xe4 = 0x00	# GPIO1 PME enable
+                                                        #irq 0xe5 = 0x00	# GPIO1 input detect select
+                                                        #irq 0xe6 = 0x40	# GPIO1 event status
+
+                                                        #irq 0xd0 = 0x00	# GPIO2 output
+                                                        #irq 0xd1 = 0xff	# GPIO2 output data
+                                                        #irq 0xd3 = 0x00	# GPIO2 drive enable
+
+                                                        #irq 0xc0 = 0x00	# GPIO3 output
+                                                        #irq 0xc1 = 0xff	# GPIO3 output data
+
+                                                        #irq 0xb0 = 0x04	# GPIO4 output
+                                                        #irq 0xb1 = 0x04	# GPIO4 output data
+                                                        #irq 0xb3 = 0x04	# GPIO4 drive enable
+                                                        #irq 0xb4 = 0x00	# GPIO4 PME enable
+                                                        #irq 0xb5 = 0x00	# GPIO4 input detect select
+                                                        #irq 0xb6 = 0x00	# GPIO4 event status
+
+                                                        #irq 0xa0 = 0x00	# GPIO5 output
+                                                        #irq 0xa1 = 0x1f	# GPIO5 output data
+                                                        #irq 0xa3 = 0x00	# GPIO5 drive enable
+                                                        #irq 0xa4 = 0x00	# GPIO5 PME enable
+                                                        #irq 0xa5 = 0xff	# GPIO5 input detect select
+                                                        #irq 0xa6 = 0xe0	# GPIO5 event status
+
+                                                        #irq 0x90 = 0x00	# GPIO6 output
+                                                        #irq 0x91 = 0xff	# GPIO6 output data
+                                                        #irq 0x93 = 0x00	# GPIO6 drive enable
+
+                                                        #irq 0x80 = 0x00	# GPIO7 output
+                                                        #irq 0x81 = 0xff	# GPIO7 output data
+                                                        #irq 0x83 = 0x00	# GPIO7 drive enable
+                                                end
+
+						device pnp 4e.07 on end	# WDT
+						device pnp 4e.08 off end	# CIR
+						device pnp 4e.0a on end	# PME
+					end # f71869ad
 				end	#device pci 14.3 # LPC
-				device pci 14.4 on  end # PCI 0x4384
-				device pci 14.5 on  end # USB 2
+				device pci 14.4 on  end # PCI 0x4384 (PCI slot on board)
+				device pci 14.5 on  end # USB OHCI
 				device pci 14.6 off end # Gec
 				device pci 14.7 off end # SD
-				device pci 15.0 on end # PCIe 0 - onboard PCIe 1x
-				device pci 15.1 on end # PCIe 1 onboard gigabit
+				device pci 15.0 off end # unused
+				device pci 15.1 off end # unused
 				device pci 15.2 off end # unused
 				device pci 15.3 off end # unused
 
diff --git a/src/mainboard/msi/ms7721/dsdt.asl b/src/mainboard/msi/ms7721/dsdt.asl
index 0028855c94..f1840f64b6 100644
--- a/src/mainboard/msi/ms7721/dsdt.asl
+++ b/src/mainboard/msi/ms7721/dsdt.asl
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2012 Advanced Micro Devices, Inc.
  * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ * Copyright (C) 2016 Renze Nicolai <renze@rnplus.nl>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -19,12 +20,12 @@ DefinitionBlock (
 	"DSDT.AML",		/* Output filename */
 	"DSDT",			/* Signature */
 	0x02,			/* DSDT Revision, needs to be 2 for 64bit */
-	"ASUS  ",		/* OEMID */
+	"MSI   ",		/* OEMID */
 	"COREBOOT",		/* TABLE ID */
 	0x00010001		/* OEM Revision */
 	)
 {	/* Start of ASL file */
-	/* #include <arch/x86/acpi/debug.asl> */	/* Include global debug methods if needed */
+	#include <arch/x86/acpi/debug.asl>	/* Include global debug methods if needed */
 
 	/* Globals for the platform */
 	#include "acpi/mainboard.asl"
@@ -61,33 +62,14 @@ DefinitionBlock (
 
 			/* Describe the AMD Fusion Controller Hub Southbridge */
 			#include <southbridge/amd/agesa/hudson/acpi/fch.asl>
-
-			/**
-			 * TODO: The devices listed here (SBR0 and SBR1) do not appear to
-			 *       be referenced anywhere and could possibly be removed.
-			 */
-			Device(SBR0) { /* PCIe 1x SB */
-				Name(_ADR, 0x00150000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(ABR0) }   /* APIC mode */
-					Return (PBR0)              /* PIC mode  */
-				}
-			}
-
-			Device(SBR1) { /* Onboard network */
-				Name(_ADR, 0x00150001)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT, 0) {
-					If(PMOD){ Return(ABR1) }   /* APIC mode */
-					Return (PBR1)              /* PIC mode  */
-				}
-			}
 		}
 
 		/* Describe PCI INT[A-H] for the Southbridge */
 		#include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
 
+		/* Describe USB for the Southbridge */
+		#include <southbridge/amd/agesa/hudson/acpi/usb.asl>
+
 	}   /* End Scope(_SB)  */
 
 	/* Describe SMBUS for the Southbridge */
diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c
index 0c30439d0f..599187d4c0 100644
--- a/src/mainboard/msi/ms7721/romstage.c
+++ b/src/mainboard/msi/ms7721/romstage.c
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2012 Advanced Micro Devices, Inc.
  * Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2016 Renze Nicolai <renze@rnplus.nl>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -31,18 +32,81 @@
 #include <device/pnp_def.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
 #include <southbridge/amd/agesa/hudson/smbus.h>
+
+#include <superio/fintek/common/fintek.h>
+#include <superio/fintek/f71869ad/f71869ad.h>
+
 #include <stdint.h>
 #include <string.h>
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8728f/it8728f.h>
 
 #define MMIO_NON_POSTED_START 0xfed00000
 #define MMIO_NON_POSTED_END   0xfedfffff
 #define SB_MMIO 0xFED80000
 #define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x))
 
-#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1)
-#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO)
+/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */
+#define SUPERIO_ADDRESS 0x4e
+
+#define SERIAL_DEV PNP_DEV(SUPERIO_ADDRESS, F71869AD_SP1)
+#define GPIO_DEV PNP_DEV(SUPERIO_ADDRESS, F71869AD_GPIO)
+
+
+/* GPIO configuration */
+#define FINTEK_ENTRY_KEY 0x87
+static void pnp_enter_conf_state(pnp_devfn_t dev)
+{
+	u16 port = dev >> 8;
+	outb(FINTEK_ENTRY_KEY, port);
+	outb(FINTEK_ENTRY_KEY, port);
+}
+
+#define FINTEK_EXIT_KEY 0xAA
+static void pnp_exit_conf_state(pnp_devfn_t dev)
+{
+	u16 port = dev >> 8;
+	outb(FINTEK_EXIT_KEY, port);
+}
+
+static void gpio_init(pnp_devfn_t dev)
+{
+	pnp_enter_conf_state(dev);
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_write_config(dev, 0x60, 0x0a); //Base addr high
+	pnp_write_config(dev, 0x61, 0x00); //Base addr low
+	pnp_write_config(dev, 0xe0, 0x04); //GPIO1 output enable
+	pnp_write_config(dev, 0xe1, 0xff); //GPIO1 output data
+	pnp_write_config(dev, 0xe3, 0x04); //GPIO1 drive enable
+	pnp_write_config(dev, 0xe4, 0x00); //GPIO1 PME enable
+	pnp_write_config(dev, 0xe5, 0x00); //GPIO1 input detect select
+	pnp_write_config(dev, 0xe6, 0x40); //GPIO1 event status
+	pnp_write_config(dev, 0xd0, 0x00); //GPIO2 output enable
+	pnp_write_config(dev, 0xd1, 0xff); //GPIO2 output data
+	pnp_write_config(dev, 0xd3, 0x00); //GPIO2 drive enable
+	pnp_write_config(dev, 0xc0, 0x00); //GPIO3 output enable
+	pnp_write_config(dev, 0xc1, 0xff); //GPIO3 output data
+	pnp_write_config(dev, 0xb0, 0x04); //GPIO4 output enable
+	pnp_write_config(dev, 0xb1, 0x04); //GPIO4 output data
+	pnp_write_config(dev, 0xb3, 0x04); //GPIO4 drive enable
+	pnp_write_config(dev, 0xb4, 0x00); //GPIO4 PME enable
+	pnp_write_config(dev, 0xb5, 0x00); //GPIO4 input detect select
+	pnp_write_config(dev, 0xb6, 0x00); //GPIO4 event status
+	pnp_write_config(dev, 0xa0, 0x00); //GPIO5 output enable
+	pnp_write_config(dev, 0xa1, 0x1f); //GPIO5 output data
+	pnp_write_config(dev, 0xa3, 0x00); //GPIO5 drive enable
+	pnp_write_config(dev, 0xa4, 0x00); //GPIO5 PME enable
+	pnp_write_config(dev, 0xa5, 0xff); //GPIO5 input detect select
+	pnp_write_config(dev, 0xa6, 0xe0); //GPIO5 event status
+	pnp_write_config(dev, 0x90, 0x00); //GPIO6 output enable
+	pnp_write_config(dev, 0x91, 0xff); //GPIO6 output data
+	pnp_write_config(dev, 0x93, 0x00); //GPIO6 drive enable
+	pnp_write_config(dev, 0x80, 0x00); //GPIO7 output enable
+	pnp_write_config(dev, 0x81, 0xff); //GPIO7 output data
+	pnp_write_config(dev, 0x83, 0x00); //GPIO7 drive enable
+	pnp_set_enable(dev, 1);
+	pnp_exit_conf_state(dev);
+}
+
 
 static void sbxxx_enable_48mhzout(void)
 {
@@ -94,9 +158,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 		/* enable SIO clock */
 		sbxxx_enable_48mhzout();
-		ite_kill_watchdog(GPIO_DEV);
-		ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-		ite_enable_3vsbsw(GPIO_DEV);
+
+		/* Initialize GPIO registers */
+		gpio_init(GPIO_DEV);
+
+		/* Enable serial console */
+		fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 		console_init();
 
 		/* turn on secondary smbus at b20 */
@@ -129,12 +196,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		disable_cache_as_ram();
 	} else {		/* S3 detect */
 		printk(BIOS_INFO, "S3 detected\n");
-
 		post_code(0x60);
 		agesawrapper_amdinitresume();
 		amd_initcpuio();
 		agesawrapper_amds3laterestore();
-
 		post_code(0x61);
 		prepare_for_resume();
 	}