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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-21 17:29:59 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-21 17:29:59 +0000 |
| commit | 57b2ff886e0ce2c92820f5722c8031def3ac94cf (patch) | |
| tree | 3bf95eb33cd3de0b8f2bae495b3ae1453601c4d3 /src/mainboard/msi/ms9185 | |
| parent | 5244e1ba63e5f3ea12066734bfb0d864a8f1f11d (diff) | |
| download | coreboot-57b2ff886e0ce2c92820f5722c8031def3ac94cf.tar.xz | |
Drop excessive whitespace randomly sprinkled in romstage.c files.
Also drop some dead or useless code snippets.
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/msi/ms9185')
| -rw-r--r-- | src/mainboard/msi/ms9185/romstage.c | 22 |
1 files changed, 5 insertions, 17 deletions
diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index 5756b4c1c8..5c52dd29dd 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -33,7 +33,6 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> - #include <cpu/amd/model_fxx_rev.h> #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" #include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c" @@ -41,19 +40,17 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include <reset.h> - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include "superio/nsc/pc87417/pc87417_early_serial.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" - #include "northbridge/amd/amdk8/setup_resource_map.c" +#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c" #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1) #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC) -#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c" static void memreset(int controllers, const struct mem_controller *ctrl) { @@ -88,24 +85,17 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" - - /* msi does not want the default */ -#include "resourcemap.c" - +#include "resourcemap.c" /* msi does not want the default */ #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> - -#define RC0 (0x10<<8) -#define RC1 (0x01<<8) - #include "cpu/amd/car/post_cache_as_ram.c" - #include "cpu/amd/model_fxx/init_cpus.c" - #include "cpu/amd/model_fxx/fidvid.c" - #include "northbridge/amd/amdk8/early_ht.c" +#define RC0 (0x10<<8) +#define RC1 (0x01<<8) + void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { @@ -260,6 +250,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif post_cache_as_ram(); - } - |