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| author | Stefan Reinauer <stepan@coresystems.de> | 2010-03-29 22:08:01 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-03-29 22:08:01 +0000 |
| commit | 798ef2893c44ce3194c539c8c5db33d11e8edbac (patch) | |
| tree | 405318f804b41070e16ca6b907d65a1e27cc5071 /src/mainboard/msi/ms9185 | |
| parent | 72bdfeb6987f9578ac7fee3f21140ab5853d6179 (diff) | |
| download | coreboot-798ef2893c44ce3194c539c8c5db33d11e8edbac.tar.xz | |
This drops the ASSEMBLY define from romstage.c, too
(since it's not assembly code, this was a dirty hack anyways)
Also run
awk 1 RS= ORS="\n\n" < $FILE > $FILE.nonewlines
mv $FILE.nonewlines $FILE
on romstage.c because my perl -pi -e 's,#define ASSEMBLY 1,,g' */*/romstage.c
cut some holes into the source.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/msi/ms9185')
| -rw-r--r-- | src/mainboard/msi/ms9185/romstage.c | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index d0b7ebde77..cf625e5561 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -23,9 +23,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 @@ -72,7 +69,6 @@ static void post_code(uint8_t value) { #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" @@ -112,8 +108,6 @@ static inline void change_i2c_mux(unsigned device) } #endif - - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); @@ -145,7 +139,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define DIMM6 0x56 #define DIMM7 0x57 - #include "cpu/amd/car/copy_and_run.c" #include "cpu/amd/car/post_cache_as_ram.c" @@ -231,7 +224,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) bcm5785_early_setup(); - #if 0 //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. needs_reset = optimize_link_coherent_ht(); @@ -315,5 +307,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); - } + |