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authorUwe Hermann <uwe@hermann-uwe.de>2010-12-05 22:36:14 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-12-05 22:36:14 +0000
commit3a4ed157dcd93f845b92fcea272368bdc41d7a11 (patch)
treea38b6e622ebae084de6965d3bc0560f4fbaea5fa /src/mainboard/msi/ms9282
parente55eb97f4a6c4ce77d0884aaf1adcb0b29e240bf (diff)
downloadcoreboot-3a4ed157dcd93f845b92fcea272368bdc41d7a11.tar.xz
W83627DHG/W83627EHG fixups for virtual LDNs.
W83627DHG: - Add proper "virtual LDN" handling for the LDNs that need it (i.e., those that don't have their "enable" bit in bit 0 of the 0x30 register). - Fix various I/O masks in the pnp_dev_info[] array as per datasheet. Add missing PNP_IRQ0 to the W83627DHG_ACPI LDN. W83627EHG: - Similar to W83627DHG, improve the "virtual LDN" setup a bit (it was mostly implemented already, though). - Add missing PNP_IRQ0 to the W83627EHG_ACPI LDN. Also: Fix up devicetree.cb of all boards using W83627DHG/W83627EHG to adapt for the virtual LDNs. include/device/pnp.h: Add comment that 'function' (which refers to the LDN and should probably be renamed later) has to be at least 16 bits wide. In theory LDNs could use u8, but due to the virtual LDN info being encoded in the "high byte" of 'function' it must be at least u16. asrock/939a785gmh/romstage.c: Drop unused GPIO6_DEV. ibase/mb899/romstage.c: Use DUMMY_DEV instead of a specific LDN (serial port 1 in this case) to avoid confusion. The global registers manipulated there are accessible from any LDN. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6140 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/msi/ms9282')
-rw-r--r--src/mainboard/msi/ms9282/devicetree.cb23
1 files changed, 18 insertions, 5 deletions
diff --git a/src/mainboard/msi/ms9282/devicetree.cb b/src/mainboard/msi/ms9282/devicetree.cb
index a4a4f6563c..74ea1832ee 100644
--- a/src/mainboard/msi/ms9282/devicetree.cb
+++ b/src/mainboard/msi/ms9282/devicetree.cb
@@ -28,22 +28,35 @@ chip northbridge/amd/amdk8/root_complex # Root complex
io 0x60 = 0x2f8
irq 0x70 = 3
end
- device pnp 2e.5 on # PS/2 keyboard
+ device pnp 2e.5 on # PS/2 keyboard & mouse
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
- device pnp 2e.6 off # Serial flash
+ device pnp 2e.106 off # Serial flash interface (SFI)
io 0x60 = 0x100
end
- device pnp 2e.7 off # Game port, MIDI, GPIO1
+ device pnp 2e.007 off # GPIO 1
+ end
+ device pnp 2e.107 off # Game port
io 0x60 = 0x220
+ end
+ device pnp 2e.207 off # MIDI
io 0x62 = 0x300
irq 0x70 = 9
end
- device pnp 2e.8 off end # WDTO PLED
- device pnp 2e.9 off end # GPIO2, GPIO3, GPIO4, GPIO5
+ device pnp 2e.307 off # GPIO 6
+ end
+ device pnp 2e.8 off end # WDTO#, PLED
+ device pnp 2e.009 off # GPIO 2
+ end
+ device pnp 2e.109 off # GPIO 3
+ end
+ device pnp 2e.209 off # GPIO 4
+ end
+ device pnp 2e.309 off # GPIO 5
+ end
device pnp 2e.a off end # ACPI
device pnp 2e.b on # Hardware monitor
io 0x60 = 0x290