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| author | Stefan Reinauer <stepan@coresystems.de> | 2010-04-25 18:06:32 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-25 18:06:32 +0000 |
| commit | bcb8c97af94c9fc814fdbdafe5361666bf81d442 (patch) | |
| tree | d3a121678b32d7436787975292432c4975bb9f6d /src/mainboard/msi/ms9652_fam10 | |
| parent | 14b62da01ded297e12db6ed3b41778202e9aae41 (diff) | |
| download | coreboot-bcb8c97af94c9fc814fdbdafe5361666bf81d442.tar.xz | |
try to unify timing initialization across those boards that need it...
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5496 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/msi/ms9652_fam10')
| -rw-r--r-- | src/mainboard/msi/ms9652_fam10/romstage.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 0d2f80fcf8..c1cb92c8f6 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -58,6 +58,8 @@ #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" @@ -262,6 +264,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) msr=rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif + init_timer(); /* Need to use TMICT to synconize FID/VID. */ wants_reset = mcp55_early_setup_x(); |