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authorStefan Reinauer <stepan@coresystems.de>2010-03-31 14:47:43 +0000
committerStefan Reinauer <stepan@openbios.org>2010-03-31 14:47:43 +0000
commit64ed2b73451de4b655b3fdda0ff42825a165c317 (patch)
tree0faaae313a9a9edbf8b33f56fc18830ba14aa75f /src/mainboard/msi
parent5a1f5970857a5ad1fda0cf9d5945192408bf537b (diff)
downloadcoreboot-64ed2b73451de4b655b3fdda0ff42825a165c317.tar.xz
Drop \r\n and \n\r as both print_XXX and printk now do this internally.
Only some assembler files still have \r\n ... Can we move that part to C completely? Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/msi')
-rw-r--r--src/mainboard/msi/ms7135/romstage.c2
-rw-r--r--src/mainboard/msi/ms7260/ap_romstage.c2
-rw-r--r--src/mainboard/msi/ms7260/romstage.c8
-rw-r--r--src/mainboard/msi/ms9185/romstage.c8
-rw-r--r--src/mainboard/msi/ms9282/romstage.c2
5 files changed, 11 insertions, 11 deletions
diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c
index 2a6c6f368b..ac5487f92c 100644
--- a/src/mainboard/msi/ms7135/romstage.c
+++ b/src/mainboard/msi/ms7135/romstage.c
@@ -169,7 +169,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ck804_early_setup_x();
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/msi/ms7260/ap_romstage.c b/src/mainboard/msi/ms7260/ap_romstage.c
index f8ac2fec3a..246d7afc64 100644
--- a/src/mainboard/msi/ms7260/ap_romstage.c
+++ b/src/mainboard/msi/ms7260/ap_romstage.c
@@ -72,7 +72,7 @@ void hardwaremain(int ret_addr)
*/
print_debug("CODE IN CACHE ON NODE:");
print_debug_hex8(id.nodeid);
- print_debug("\r\n");
+ print_debug("\n");
train_ram(id.nodeid, sysinfo, sysinfox);
diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 7e97a27e53..846091a969 100644
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -190,7 +190,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
print_debug("bsp_apicid=");
print_debug_hex8(bsp_apicid);
- print_debug("\r\n");
+ print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1
/* In BSP so could hold all AP until sysinfo is in RAM. */
@@ -220,7 +220,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug("begin msr fid, vid ");
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
- print_debug("\r\n");
+ print_debug("\n");
}
enable_fid_change();
@@ -232,7 +232,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug("end msr fid, vid ");
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
- print_debug("\r\n");
+ print_debug("\n");
}
#endif
@@ -242,7 +242,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* fidvid change will issue one LDTSTOP and the HT change will be effective too. */
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c
index 350980e5d2..ecc95d5d67 100644
--- a/src/mainboard/msi/ms9185/romstage.c
+++ b/src/mainboard/msi/ms9185/romstage.c
@@ -204,7 +204,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+ print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
setup_coherent_ht_domain();
@@ -235,7 +235,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
@@ -249,7 +249,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
#endif
@@ -260,7 +260,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
#endif
diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c
index 24a307eff6..9e6f973c93 100644
--- a/src/mainboard/msi/ms9282/romstage.c
+++ b/src/mainboard/msi/ms9282/romstage.c
@@ -214,7 +214,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= mcp55_early_setup_x();
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}