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authorStefan Reinauer <stepan@coresystems.de>2010-04-15 23:01:59 +0000
committerStefan Reinauer <stepan@openbios.org>2010-04-15 23:01:59 +0000
commite46c1c85c90b6d263f951ab745a9fadd93041111 (patch)
tree4ffefdc0767139b66c48732d44b8a3222eb6b09f /src/mainboard/msi
parentc24d383c15f6d31cd1dd5fb8e090db0561421599 (diff)
downloadcoreboot-e46c1c85c90b6d263f951ab745a9fadd93041111.tar.xz
remove more warnings. move ROOT_COMPLEX selection to fam10
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5447 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/msi')
-rw-r--r--src/mainboard/msi/ms9282/romstage.c30
-rw-r--r--src/mainboard/msi/ms9652_fam10/Kconfig1
2 files changed, 14 insertions, 17 deletions
diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c
index c3702084e5..87517f078c 100644
--- a/src/mainboard/msi/ms9282/romstage.c
+++ b/src/mainboard/msi/ms9282/romstage.c
@@ -120,8 +120,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
@@ -151,12 +149,12 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
- // Node 0
- RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6,
- RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7,
- // node 1
- RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6,
- RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7,
+ // Node 0
+ RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6,
+ RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7,
+ // node 1
+ RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6,
+ RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7,
};
unsigned bsp_apicid = 0;
@@ -181,18 +179,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
- w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- uart_init();
- console_init();
+ w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ uart_init();
+ console_init();
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
- setup_ms9282_resource_map();
+ setup_ms9282_resource_map();
- setup_coherent_ht_domain();
+ setup_coherent_ht_domain();
- wait_all_core0_started();
+ wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig
index 4a80544342..7bbd01c683 100644
--- a/src/mainboard/msi/ms9652_fam10/Kconfig
+++ b/src/mainboard/msi/ms9652_fam10/Kconfig
@@ -3,7 +3,6 @@ config BOARD_MSI_MS9652_FAM10
select ARCH_X86
select CPU_AMD_SOCKET_F_1207
select NORTHBRIDGE_AMD_AMDFAM10
- select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
select SOUTHBRIDGE_NVIDIA_MCP55
select SUPERIO_WINBOND_W83627EHG
select HAVE_BUS_CONFIG