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authorPatrick Georgi <patrick.georgi@coresystems.de>2009-04-30 07:07:22 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2009-04-30 07:07:22 +0000
commit12aba82e55c02470ed80b7682efa8b4e8f702bc1 (patch)
treef48156a0a625fdd9d7358e6a172a5cdb343ca9a7 /src/mainboard/msi
parenta43ee75d9a7dc859292b186f22ac0550f149a0a3 (diff)
downloadcoreboot-12aba82e55c02470ed80b7682efa8b4e8f702bc1.tar.xz
Refactor copy_and_run so that it uses a single code base instead of
3 (with one of them way too much assembler code). On the way, I had to make some changes to the way the code is built, which is an effort I want to expand over time. Right now, large portions of the in-ROM part of coreboot is compiled as a single file, with lots of .c files including other .c files. That has its justification for pre-raminit code, but it also affects lots of post-raminit code (memcpy doesn't really make sense before raminit, or at least CAR) The coreboot_apc code (AMD boards) gained some .c includes because I don't know that part of the code enough to really rework it and only have limited possibilities to test it. The includes should give an identical situation for this part of the code. This change was posted as set of 6 patches to the list, but they were mostly split for review purposes, hence commit them all at once. They can still be backed up using the patch files, if necessary. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/msi')
-rw-r--r--src/mainboard/msi/ms7135/cache_as_ram_auto.c5
-rw-r--r--src/mainboard/msi/ms7260/cache_as_ram_auto.c4
-rw-r--r--src/mainboard/msi/ms9185/cache_as_ram_auto.c5
-rw-r--r--src/mainboard/msi/ms9282/cache_as_ram_auto.c5
4 files changed, 4 insertions, 15 deletions
diff --git a/src/mainboard/msi/ms7135/cache_as_ram_auto.c b/src/mainboard/msi/ms7135/cache_as_ram_auto.c
index 74c5ccc014..eaeeeb16e5 100644
--- a/src/mainboard/msi/ms7135/cache_as_ram_auto.c
+++ b/src/mainboard/msi/ms7135/cache_as_ram_auto.c
@@ -38,6 +38,7 @@
#endif
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -56,10 +57,6 @@
#define CK804_USE_NIC 1
#define CK804_USE_ACI 1
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
-
#include <cpu/amd/model_fxx_rev.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
diff --git a/src/mainboard/msi/ms7260/cache_as_ram_auto.c b/src/mainboard/msi/ms7260/cache_as_ram_auto.c
index 22b82ddedf..c9e429d5ca 100644
--- a/src/mainboard/msi/ms7260/cache_as_ram_auto.c
+++ b/src/mainboard/msi/ms7260/cache_as_ram_auto.c
@@ -50,6 +50,7 @@
#define DBGP_DEFAULT 7
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@@ -84,9 +85,6 @@
#if USE_FAILOVER_IMAGE == 0
#include "cpu/x86/bist.h"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
diff --git a/src/mainboard/msi/ms9185/cache_as_ram_auto.c b/src/mainboard/msi/ms9185/cache_as_ram_auto.c
index 437394e24a..cd7a3d236d 100644
--- a/src/mainboard/msi/ms9185/cache_as_ram_auto.c
+++ b/src/mainboard/msi/ms9185/cache_as_ram_auto.c
@@ -47,6 +47,7 @@
#define DEBUG_SMBUS 1
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@@ -75,10 +76,6 @@ static void post_code(uint8_t value) {
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
- #include "lib/memcpy.c"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
diff --git a/src/mainboard/msi/ms9282/cache_as_ram_auto.c b/src/mainboard/msi/ms9282/cache_as_ram_auto.c
index 9754f3fc60..6e8760d4bc 100644
--- a/src/mainboard/msi/ms9282/cache_as_ram_auto.c
+++ b/src/mainboard/msi/ms9282/cache_as_ram_auto.c
@@ -41,6 +41,7 @@
#define DEBUG_SMBUS 1
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -57,10 +58,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
- #include "lib/memcpy.c"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"