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authorKyösti Mälkki <kyosti.malkki@gmail.com>2017-09-23 19:10:04 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-10-19 11:24:09 +0000
commit9fee35c6c4aafd0f8c429263e24a7378dc138f02 (patch)
tree8d9b1db3b2b50161e2277d83c7f02208df93f6d2 /src/mainboard/msi
parentc700829cd3657f1840be581760ca0a2f13226238 (diff)
downloadcoreboot-9fee35c6c4aafd0f8c429263e24a7378dc138f02.tar.xz
AGESA: Split long lines in OemCustomize.c
Change-Id: I907f55622e6aaba401471239f706ab24cd26319f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Diffstat (limited to 'src/mainboard/msi')
-rw-r--r--src/mainboard/msi/ms7721/OemCustomize.c30
1 files changed, 25 insertions, 5 deletions
diff --git a/src/mainboard/msi/ms7721/OemCustomize.c b/src/mainboard/msi/ms7721/OemCustomize.c
index 80e6c96751..5377e8842d 100644
--- a/src/mainboard/msi/ms7721/OemCustomize.c
+++ b/src/mainboard/msi/ms7721/OemCustomize.c
@@ -71,31 +71,51 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lane 4, PCI Device Number 4, Realtek LAN */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lane 5, PCI Device Number 5, x1 slot (1) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lane 6, PCI Device Number 6, x1 slot (2) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0)
},
};