diff options
author | Martin Roth <martinroth@google.com> | 2017-06-24 21:54:33 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-07-06 00:20:06 +0000 |
commit | 43927bae1846e0768cbfad717f4820f408cde82b (patch) | |
tree | 3752707f9ecc93f8d125682f6dfb89896ff5db15 /src/mainboard/msi | |
parent | 356b519049e6d40e15b2e4a85cae654e2e8df8ba (diff) | |
download | coreboot-43927bae1846e0768cbfad717f4820f408cde82b.tar.xz |
mainboard/[m-w]: add IS_ENABLED() around Kconfig symbol references
Change-Id: Ifba3257b0328d0b6ad1bee9bf885683998df5851
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/msi')
-rw-r--r-- | src/mainboard/msi/ms7135/romstage.c | 6 | ||||
-rw-r--r-- | src/mainboard/msi/ms7260/romstage.c | 4 | ||||
-rw-r--r-- | src/mainboard/msi/ms7721/buildOpts.c | 2 | ||||
-rw-r--r-- | src/mainboard/msi/ms9185/mptable.c | 2 | ||||
-rw-r--r-- | src/mainboard/msi/ms9185/romstage.c | 4 | ||||
-rw-r--r-- | src/mainboard/msi/ms9282/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/msi/ms9652_fam10/romstage.c | 4 |
7 files changed, 12 insertions, 12 deletions
diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 08fbdc7e4d..c595006e14 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -41,7 +41,7 @@ #include <spd.h> #include <northbridge/amd/amdk8/pre_f.h> -#if CONFIG_HAVE_OPTION_TABLE +#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE) #include "option_table.h" #endif @@ -132,7 +132,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); @@ -156,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) ms7135_set_nf4_voltage(); ms7135_set_ram_voltage(); -#if CONFIG_DEBUG_SMBUS +#if IS_ENABLED(CONFIG_DEBUG_SMBUS) dump_spd_registers(&ctrl[0]); dump_smbus_registers(); #endif diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 6feddcfef1..5287258a18 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -144,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); /* Routing table and start other core0. */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* It is said that we should start core1 after all core0 launched * becase optimize_link_coherent_ht is moved out from * setup_coherent_ht_domain, so here need to make sure last core0 is @@ -158,7 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Set up chains and store link pair for optimization later. */ ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) { msr_t msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c index ecb168c638..5191574fef 100644 --- a/src/mainboard/msi/ms7721/buildOpts.c +++ b/src/mainboard/msi/ms7721/buildOpts.c @@ -168,7 +168,7 @@ #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 -#if CONFIG_GFXUMA +#if IS_ENABLED(CONFIG_GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c index 38cc72bbbc..e93602be1c 100644 --- a/src/mainboard/msi/ms9185/mptable.c +++ b/src/mainboard/msi/ms9185/mptable.c @@ -26,7 +26,7 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdk8_sysconf.h> diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index 56eaa6ac8b..5d031795dc 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -123,7 +123,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, @@ -144,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset |= optimize_link_incoherent_ht(sysinfo); #endif -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) { msr_t msr; msr = rdmsr(0xc0010042); diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index fd9049146a..4fa40bf0ce 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -154,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched start_other_cores(); //wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 4acb240548..11e9bc0492 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -178,7 +178,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -189,7 +189,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x38); -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); |