diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-07-30 17:46:17 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-14 19:06:25 +0200 |
| commit | 8ab989e31561cea0c6af5d5e242dd2be97bc73b4 (patch) | |
| tree | 31bc3a2175762b179d2fc093c34f62c18b15b9ee /src/mainboard/msi | |
| parent | 589ef9de8faa2db11a7ce2769fc1d9396a82886b (diff) | |
| download | coreboot-8ab989e31561cea0c6af5d5e242dd2be97bc73b4.tar.xz | |
src/mainboard: Capitalize ROM, RAM, CPU and APIC
Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15987
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/msi')
| -rw-r--r-- | src/mainboard/msi/ms7260/resourcemap.c | 2 | ||||
| -rw-r--r-- | src/mainboard/msi/ms9652_fam10/resourcemap.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/msi/ms7260/resourcemap.c b/src/mainboard/msi/ms7260/resourcemap.c index a7d520d349..f17fadf1a0 100644 --- a/src/mainboard/msi/ms7260/resourcemap.c +++ b/src/mainboard/msi/ms7260/resourcemap.c @@ -267,7 +267,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ -// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */ +// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */ PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/msi/ms9652_fam10/resourcemap.c b/src/mainboard/msi/ms9652_fam10/resourcemap.c index 76fbaa3803..610baf3631 100644 --- a/src/mainboard/msi/ms9652_fam10/resourcemap.c +++ b/src/mainboard/msi/ms9652_fam10/resourcemap.c @@ -269,7 +269,7 @@ static void setup_mb_resource_map(void) * This field defines the highest bus number in configuration region i */ /* Verified against board configuration registers after normal proprietary BIOS boot */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, |