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author | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-03-17 22:44:39 +0000 |
---|---|---|
committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-03-17 22:44:39 +0000 |
commit | ce6fb1ee2b37193fa828b4c6d475e23c58171346 (patch) | |
tree | 7207e49edde04fefd1a9208a73135d7a27c7b3dc /src/mainboard/msi | |
parent | 78b40335841eae958865f67ac8ee0020fd43aead (diff) | |
download | coreboot-ce6fb1ee2b37193fa828b4c6d475e23c58171346.tar.xz |
Remove failover/fallback/normal handling in mainboards'
romstage.c. That's newconfig stuff.
1. In failover_process(), I removed the fallback/normal selection logic
and kept the remaining hardware init in. The if-clauses' conditions are
reverted to match.
Remove #if failover||fallback guard.
2. Change cache_as_ram_main() to first call failover_process, then
real_main unconditionally.
3. Move failover_process's code to the beginning of real_main, remove
failover_process and its call in cache_as_ram_main.
4. Remove cache_as_ram_main, rename real_main to cache_as_ram_main (same
arguments, so no problem with that)
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5255 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/msi')
-rw-r--r-- | src/mainboard/msi/ms7135/romstage.c | 87 | ||||
-rw-r--r-- | src/mainboard/msi/ms7260/romstage.c | 80 | ||||
-rw-r--r-- | src/mainboard/msi/ms9652_fam10/romstage.c | 86 |
3 files changed, 38 insertions, 215 deletions
diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 9477c6e514..6fc010ddf1 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -100,9 +100,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #endif /* CONFIG_USE_FAILOVER_IMAGE */ -#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) \ - || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) - #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -124,79 +121,8 @@ static void sio_setup(void) pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword); } -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a CPU only reset? Or is this a secondary CPU? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the ck804 */ - ck804_enable_rom(); - - /* Is this a deliberate reset by the BIOS? */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - - /* This is the primary CPU. How should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } - -normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */ - ); - -fallback_image: - -#if CONFIG_HAVE_FAILOVER_BOOT == 1 - __asm__ volatile ("jmp __fallback_image" - : /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */ - ) -#endif - ; -} - -#endif /* ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) ... */ - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ -#if CONFIG_HAVE_FAILOVER_BOOT == 1 -#if CONFIG_USE_FAILOVER_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#else - real_main(bist, cpu_init_detectedx); -#endif -#else -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -#endif -} - #if CONFIG_USE_FAILOVER_IMAGE == 0 -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { (0xa << 3) | 0, (0xa << 3) | 1, 0, 0, @@ -211,6 +137,17 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) struct mem_controller ctrl[8]; unsigned nodes; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the ck804 */ + ck804_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); } diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index a8697b5114..ee63d149ba 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -131,8 +131,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #endif -#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -154,74 +152,9 @@ static void sio_setup(void) pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword); } -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned int last_boot_normal_x = last_boot_normal(); - - /* Is this a CPU only reset? Or is this a secondary CPU? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) - goto normal_image; - else - goto fallback_image; - } - - /* Nothing special needs to be done to find bus 0. */ - /* Allow the HT devices to be found. */ - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the MCP55. */ - mcp55_enable_rom(); - - /* Is this a deliberate reset by the BIOS? */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary CPU. How should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } - -normal_image: - __asm__ volatile ("jmp __normal_image": - :"a" (bist), "b"(cpu_init_detectedx) - ); - -fallback_image: -#if CONFIG_HAVE_FAILOVER_BOOT==1 - __asm__ volatile ("jmp __fallback_image": - :"a" (bist), "b"(cpu_init_detectedx) - ) -#endif - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ -#if CONFIG_HAVE_FAILOVER_BOOT == 1 -#if CONFIG_USE_FAILOVER_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#else - real_main(bist, cpu_init_detectedx); -#endif -#else -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -#endif -} - #if CONFIG_USE_FAILOVER_IMAGE == 0 -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { (0xa << 3) | 0, (0xa << 3) | 2, 0, 0, @@ -237,6 +170,17 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) int needs_reset = 0; unsigned bsp_apicid = 0; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0. */ + /* Allow the HT devices to be found. */ + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the MCP55. */ + mcp55_enable_rom(); + } + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 60a1e14f1d..16925256d5 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -145,8 +145,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #endif -#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -165,81 +163,12 @@ static void sio_setup(void) pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); } -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the mcp55 */ - mcp55_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -#if CONFIG_HAVE_FAILOVER_BOOT==1 - __asm__ volatile ("jmp __fallback_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ) -#endif - ; -} -#endif -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ -#if CONFIG_HAVE_FAILOVER_BOOT==1 - #if CONFIG_USE_FAILOVER_IMAGE==1 - failover_process(bist, cpu_init_detectedx); - #else - real_main(bist, cpu_init_detectedx); - #endif -#else - #if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); - #endif - real_main(bist, cpu_init_detectedx); -#endif -} - #if CONFIG_USE_FAILOVER_IMAGE==0 #include "spd_addr.h" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); @@ -249,6 +178,19 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 wants_reset; msr_t msr; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + set_bsp_node_CHtExtNodeCfgEn(); + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the mcp55 */ + mcp55_enable_rom(); + } + post_code(0x30); if (bist == 0) { |