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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-20 06:43:47 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-03-28 07:06:07 +0200
commitfd22b0847379fac6ef847aeef0de183fd50a9ca2 (patch)
tree4a14c92480b42cc7d4b2f6cfb7e4642ff1259549 /src/mainboard/msi
parent24b6a26ca95337fd8f9c7d95792d6cd40319d658 (diff)
downloadcoreboot-fd22b0847379fac6ef847aeef0de183fd50a9ca2.tar.xz
msi/ms7721: Switch away from AGESA_LEGACY
Change-Id: I0322fb69455cf6e196c0f6c6221bef806f1aa989 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18713 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/msi')
-rw-r--r--src/mainboard/msi/ms7721/Kconfig1
-rw-r--r--src/mainboard/msi/ms7721/romstage.c136
2 files changed, 36 insertions, 101 deletions
diff --git a/src/mainboard/msi/ms7721/Kconfig b/src/mainboard/msi/ms7721/Kconfig
index 1fe6dd2079..7a2623b80b 100644
--- a/src/mainboard/msi/ms7721/Kconfig
+++ b/src/mainboard/msi/ms7721/Kconfig
@@ -20,7 +20,6 @@ if BOARD_MSI_MS7721
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
- select AGESA_LEGACY
select CPU_AMD_AGESA_FAMILY15_TN
select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
select SOUTHBRIDGE_AMD_AGESA_HUDSON
diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c
index 5f769b3b65..b82dfa67c4 100644
--- a/src/mainboard/msi/ms7721/romstage.c
+++ b/src/mainboard/msi/ms7721/romstage.c
@@ -15,31 +15,18 @@
* GNU General Public License for more details.
*/
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-
-#include <arch/acpi.h>
-#include <arch/cpu.h>
#include <arch/io.h>
-#include <arch/stages.h>
-#include <cbmem.h>
#include <console/console.h>
-#include <cpu/amd/agesa/s3_resume.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <device/pnp_def.h>
+#include <device/pnp.h>
+#include <stdint.h>
+
+#include <northbridge/amd/agesa/state_machine.h>
#include <southbridge/amd/common/amd_defs.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
-#include <southbridge/amd/agesa/hudson/smbus.h>
#include <superio/fintek/common/fintek.h>
#include <superio/fintek/f71869ad/f71869ad.h>
-#include <stdint.h>
-#include <string.h>
#define MMIO_NON_POSTED_START 0xfed00000
#define MMIO_NON_POSTED_END 0xfedfffff
@@ -123,91 +110,40 @@ static void sbxxx_enable_48mhzout(void)
SB_MMIO_MISC32(0x40) = reg32;
}
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+
+void board_BeforeAgesa(struct sysinfo *cb)
{
- u32 val;
u8 byte;
pci_devfn_t dev;
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
-#if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)
- hudson_pci_port80();
-#endif
-#if IS_ENABLED(CONFIG_POST_DEVICE_LPC)
- hudson_lpc_port80();
-#endif
-
- if (!cpu_init_detectedx && boot_cpu()) {
-
- /* enable SIO LPC decode */
- dev = PCI_DEV(0, 0x14, 3);
- byte = pci_read_config8(dev, 0x48);
- byte |= 3; /* 2e, 2f */
- pci_write_config8(dev, 0x48, byte);
-
- /* enable serial decode */
- byte = pci_read_config8(dev, 0x44);
- byte |= (1 << 6); /* 0x3f8 */
- pci_write_config8(dev, 0x44, byte);
-
- post_code(0x30);
-
- /* enable SB MMIO space */
- outb(0x24, 0xcd6);
- outb(0x1, 0xcd7);
-
- /* enable SIO clock */
- sbxxx_enable_48mhzout();
-
- /* Initialize GPIO registers */
- gpio_init(GPIO_DEV);
-
- /* Enable serial console */
- fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* turn on secondary smbus at b20 */
- outb(0x28, 0xcd6);
- byte = inb(0xcd7);
- byte |= 1;
- outb(byte, 0xcd7);
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- post_code(0x37);
- agesawrapper_amdinitreset();
- post_code(0x39);
-
- agesawrapper_amdinitearly();
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- agesawrapper_amdinitpost();
- post_code(0x41);
- agesawrapper_amdinitenv();
- disable_cache_as_ram();
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
- post_code(0x60);
- agesawrapper_amdinitresume();
- amd_initcpuio();
- agesawrapper_amds3laterestore();
- post_code(0x61);
- prepare_for_resume();
- }
-
- post_code(0x50);
- copy_and_run();
-
- post_code(0x54); /* Should never see this post code. */
+ if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE))
+ hudson_pci_port80();
+ else if (IS_ENABLED(CONFIG_POST_DEVICE_LPC))
+ hudson_lpc_port80();
+
+ /* enable SIO LPC decode */
+ dev = PCI_DEV(0, 0x14, 3);
+ byte = pci_read_config8(dev, 0x48);
+ byte |= 3; /* 2e, 2f */
+ pci_write_config8(dev, 0x48, byte);
+
+ /* enable serial decode */
+ byte = pci_read_config8(dev, 0x44);
+ byte |= (1 << 6); /* 0x3f8 */
+ pci_write_config8(dev, 0x44, byte);
+
+ post_code(0x30);
+
+ /* enable SB MMIO space */
+ outb(0x24, 0xcd6);
+ outb(0x1, 0xcd7);
+
+ /* enable SIO clock */
+ sbxxx_enable_48mhzout();
+
+ /* Initialize GPIO registers */
+ gpio_init(GPIO_DEV);
+
+ /* Enable serial console */
+ fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}