Drop W83627THF, it's the same device as W83627THG.

The only difference is that the "G" version is in a Pb-free package, which
is not relevant from a programmer's view.

We keep W83627THG (and drop W83627THF) because:

 - The W83627THF had a CIR device / LDN which doesn't actually exist.

 - The W83627THF had no GPIO2, GPIO3 LDNs (were commented out).

 - The W83627THF didn't use the PNP_MSC0/1 which is needed/used by boards.

This also fixes an issue on MSI MS7135's devicetree.cb:

  device pnp 4e.6 off end           # XXX keep allocator happy

The line above can be (and is) removed, as it was only needed due to the
incorrect CIR LDN in the W83627THF.

In the iwill/dk8x target: Drop incorrect LDNs 4 and 6, add 0xb.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 7 insertions, 8 deletions

diff --git a/src/mainboard/msi/ms7135/Kconfig b/src/mainboard/msi/ms7135/Kconfig
index 2de546b730..d8581f731c 100644
--- a/src/mainboard/msi/ms7135/Kconfig
+++ b/src/mainboard/msi/ms7135/Kconfig
@@ -7,7 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_AMD_AMDK8
 	select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
 	select SOUTHBRIDGE_NVIDIA_CK804
-	select SUPERIO_WINBOND_W83627THF
+	select SUPERIO_WINBOND_W83627THG
 	select HAVE_BUS_CONFIG
 	select HAVE_HARD_RESET
 	select HAVE_OPTION_TABLE
diff --git a/src/mainboard/msi/ms7135/devicetree.cb b/src/mainboard/msi/ms7135/devicetree.cb
index e796b94650..14c6bad1d3 100644
--- a/src/mainboard/msi/ms7135/devicetree.cb
+++ b/src/mainboard/msi/ms7135/devicetree.cb
@@ -11,7 +11,7 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
         chip southbridge/nvidia/ck804		# Southbridge
           device pci 0.0 on end			# HT
           device pci 1.0 on			# LPC
-            chip superio/winbond/w83627thf	# Super I/O
+            chip superio/winbond/w83627thg	# Super I/O
               device pnp 4e.0 on		# Floppy
                 io 0x60 = 0x3f0
                 irq 0x70 = 6
@@ -30,14 +30,13 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
                 io 0x60 = 0x2f8
                 irq 0x70 = 3
               end
-              device pnp 4e.5 on		# PS/2 keyboard
+              device pnp 4e.5 on		# PS/2 keyboard & mouse
                 io 0x60 = 0x60
                 io 0x62 = 0x64
                 irq 0x70 = 1
                 irq 0x72 = 12
               end
-              device pnp 4e.6 off end		# XXX keep allocator happy
-              device pnp 4e.7 off end		# Game, MIDI, GPIO 1, GPIO 5
+              device pnp 4e.7 off end		# Game port, MIDI, GPIO 1 & 5
               device pnp 4e.8 off end		# GPIO 2
               device pnp 4e.9 off end		# GPIO 3, GPIO 4
               device pnp 4e.a off end		# ACPI
diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c
index a4b9cb6567..f6dbb0ae6d 100644
--- a/src/mainboard/msi/ms7135/romstage.c
+++ b/src/mainboard/msi/ms7135/romstage.c
@@ -22,7 +22,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define SERIAL_DEV PNP_DEV(0x4e, W83627THF_SP1)
+#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
 
 #if CONFIG_LOGICAL_CPUS == 1
 #define SET_NB_CFG_54 1
@@ -38,7 +38,7 @@
 #include <pc80/mc146818rtc.h>
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/winbond/w83627thf/w83627thf_early_serial.c"
+#include "superio/winbond/w83627thg/w83627thg_early_serial.c"
 
 #include <cpu/amd/model_fxx_rev.h>
 #include <console/console.h>
@@ -123,7 +123,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		bsp_apicid = init_cpus(cpu_init_detectedx);
 	}
 
-	w83627thf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();