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| author | Stefan Reinauer <stepan@openbios.org> | 2003-10-24 13:53:33 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2003-10-24 13:53:33 +0000 |
| commit | e4436bd7f640170c03798914baa2c47690df5e61 (patch) | |
| tree | 4e30ab2bcf5fcb034a52708f908631b92142bd7d /src/mainboard/newisys/khepri/Config.lb | |
| parent | a9974e584cb6fa9baabc89145920403b98fbc930 (diff) | |
| download | coreboot-e4436bd7f640170c03798914baa2c47690df5e61.tar.xz | |
retightening khepri after last hdama changes
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1230 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/newisys/khepri/Config.lb')
| -rw-r--r-- | src/mainboard/newisys/khepri/Config.lb | 64 |
1 files changed, 34 insertions, 30 deletions
diff --git a/src/mainboard/newisys/khepri/Config.lb b/src/mainboard/newisys/khepri/Config.lb index 76c7874001..c58211a69b 100644 --- a/src/mainboard/newisys/khepri/Config.lb +++ b/src/mainboard/newisys/khepri/Config.lb @@ -15,6 +15,9 @@ uses _ROMBASE uses XIP_ROM_SIZE uses XIP_ROM_BASE +## ROM_SIZE is the size of boot ROM that this board will use. +default ROM_SIZE 524288 + ### ### Build options ### @@ -68,9 +71,6 @@ option MAINBOARD_VENDOR="NEWISYS" ### LinuxBIOS layout values ### -## ROM_SIZE is the size of boot ROM that this board will use. -option ROM_SIZE = 524288 - ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. option ROM_IMAGE_SIZE = 65536 @@ -150,7 +150,7 @@ end makerule ./failover.inc depends "./failover.E ./romcc" - action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E" + action "./romcc -O2 -o failover.inc --label-prefix=failover ./failover.E" end makerule ./auto.E @@ -159,7 +159,7 @@ makerule ./auto.E end makerule ./auto.inc depends "./auto.E ./romcc" - action "./romcc -mcpu=k8 -O ./auto.E > auto.inc" + action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc" end ## @@ -229,32 +229,36 @@ northbridge amd/amdk8 "mc0" pci 0:18.1 pci 0:18.2 pci 0:18.3 - southbridge amd/amd8131 "amd8131" - pci 1:0.0 - pci 1:0.1 - pci 1:1.0 - pci 1:1.1 + southbridge amd/amd8131 "amd8131" link 1 + pci 0:0.0 + pci 0:0.1 + pci 0:1.0 + pci 0:1.1 end - southbridge amd/amd8111 "amd8111" - pci 1:0.0 - pci 1:1.0 - pci 1:1.1 - pci 1:1.2 - pci 1:1.3 - pci 1:1.5 - pci 1:1.6 - superio NSC/pc87360 - pnp 1:2e.0 - pnp 1:2e.1 - pnp 1:2e.2 - pnp 1:2e.3 - pnp 1:2e.4 - pnp 1:2e.5 - pnp 1:2e.6 - pnp 1:2e.7 - pnp 1:2e.8 - pnp 1:2e.9 - pnp 1:2e.a + southbridge amd/amd8111 "amd8111" link 1 + pci 0:0.0 + pci 0:1.0 on + pci 0:1.1 on + pci 0:1.2 on + pci 0:1.3 on + pci 0:1.5 on + pci 0:1.6 on + pci 1:0.0 on + pci 1:0.1 on + pci 1:0.2 on + pci 1:1.0 on + superio NSC/pc87360 link 1 + pnp 2e.0 + pnp 2e.1 + pnp 2e.2 + pnp 2e.3 + pnp 2e.4 + pnp 2e.5 + pnp 2e.6 + pnp 2e.7 + pnp 2e.8 + pnp 2e.9 + pnp 2e.a register "com1" = "{1, 0, 0x3f8, 4}" register "lpt" = "{1}" end |