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author | Stefan Reinauer <stepan@openbios.org> | 2003-08-28 17:23:15 +0000 |
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committer | Stefan Reinauer <stepan@openbios.org> | 2003-08-28 17:23:15 +0000 |
commit | b980e39c81a1eed2dc3e2d1a939320292b36885c (patch) | |
tree | 857194fa2ea1078add319df58ed998cf67b13749 /src/mainboard/newisys/khepri/failover.c | |
parent | f4440e65a45aaa7d05ea55a8304630d7fd31ac44 (diff) | |
download | coreboot-b980e39c81a1eed2dc3e2d1a939320292b36885c.tar.xz |
add first bunch of newisys khepri files.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1090 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/newisys/khepri/failover.c')
-rw-r--r-- | src/mainboard/newisys/khepri/failover.c | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/src/mainboard/newisys/khepri/failover.c b/src/mainboard/newisys/khepri/failover.c new file mode 100644 index 0000000000..8eeeaef7e1 --- /dev/null +++ b/src/mainboard/newisys/khepri/failover.c @@ -0,0 +1,38 @@ +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include "arch/romcc_io.h" +#include "pc80/mc146818rtc_early.c" +#include "southbridge/amd/amd8111/amd8111_enable_rom.c" +#include "northbridge/amd/amdk8/early_ht.c" +#include "cpu/p6/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" + +static void main(void) +{ + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(0); + + /* Setup the 8111 */ + amd8111_enable_rom(); + + /* Is this a cpu reset? */ + if (cpu_init_detected()) { + if (last_boot_normal()) { + asm("jmp __normal_image"); + } else { + asm("jmp __cpu_reset"); + } + } + /* Is this a secondary cpu? */ + else if (!boot_cpu() && last_boot_normal()) { + asm("jmp __normal_image"); + } + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + asm("jmp __normal_image"); + } +} |