retightening khepri after last hdama changes

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1230 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

6 files changed, 131 insertions, 113 deletions

diff --git a/src/mainboard/newisys/khepri/Config.lb b/src/mainboard/newisys/khepri/Config.lb
index 76c7874001..c58211a69b 100644
--- a/src/mainboard/newisys/khepri/Config.lb
+++ b/src/mainboard/newisys/khepri/Config.lb
@@ -15,6 +15,9 @@ uses _ROMBASE
 uses XIP_ROM_SIZE
 uses XIP_ROM_BASE
 
+## ROM_SIZE is the size of boot ROM that this board will use.
+default ROM_SIZE 524288
+
 ###
 ### Build options
 ###
@@ -68,9 +71,6 @@ option MAINBOARD_VENDOR="NEWISYS"
 ### LinuxBIOS layout values
 ###
 
-## ROM_SIZE is the size of boot ROM that this board will use.
-option ROM_SIZE = 524288
-
 ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
 option ROM_IMAGE_SIZE = 65536
 
@@ -150,7 +150,7 @@ end
 
 makerule ./failover.inc
 	depends "./failover.E ./romcc"
-	action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
+	action "./romcc -O2 -o failover.inc --label-prefix=failover ./failover.E"
 end
 
 makerule ./auto.E 
@@ -159,7 +159,7 @@ makerule ./auto.E
 end
 makerule ./auto.inc 
 	depends "./auto.E ./romcc"
-	action	"./romcc -mcpu=k8  -O ./auto.E > auto.inc"
+	action	"./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
 end
 
 ##
@@ -229,32 +229,36 @@ northbridge amd/amdk8 "mc0"
 	pci 0:18.1
 	pci 0:18.2
 	pci 0:18.3
-	southbridge amd/amd8131 "amd8131"
-		pci 1:0.0
-		pci 1:0.1
-		pci 1:1.0
-		pci 1:1.1
+	southbridge amd/amd8131 "amd8131" link 1
+		pci 0:0.0
+		pci 0:0.1
+		pci 0:1.0
+		pci 0:1.1
 	end
-	southbridge amd/amd8111 "amd8111"
-		pci 1:0.0
-		pci 1:1.0
-		pci 1:1.1
-		pci 1:1.2
-		pci 1:1.3
-		pci 1:1.5
-		pci 1:1.6
-		superio NSC/pc87360
-			pnp 1:2e.0
-			pnp 1:2e.1
-			pnp 1:2e.2
-			pnp 1:2e.3
-			pnp 1:2e.4
-			pnp 1:2e.5
-			pnp 1:2e.6
-			pnp 1:2e.7
-			pnp 1:2e.8
-			pnp 1:2e.9
-			pnp 1:2e.a
+	southbridge amd/amd8111 "amd8111" link 1
+		pci 0:0.0
+		pci 0:1.0 on
+		pci 0:1.1 on
+		pci 0:1.2 on
+		pci 0:1.3 on
+		pci 0:1.5 on
+		pci 0:1.6 on
+		pci 1:0.0 on
+		pci 1:0.1 on
+		pci 1:0.2 on
+		pci 1:1.0 on
+		superio NSC/pc87360 link 1
+			pnp 2e.0
+			pnp 2e.1
+			pnp 2e.2
+			pnp 2e.3
+			pnp 2e.4
+			pnp 2e.5
+			pnp 2e.6
+			pnp 2e.7
+			pnp 2e.8
+			pnp 2e.9
+			pnp 2e.a
 			register "com1" = "{1, 0, 0x3f8, 4}"
 			register "lpt" = "{1}"
 		end
diff --git a/src/mainboard/newisys/khepri/auto.c b/src/mainboard/newisys/khepri/auto.c
index 3d28fa728d..35160b2b95 100644
--- a/src/mainboard/newisys/khepri/auto.c
+++ b/src/mainboard/newisys/khepri/auto.c
@@ -1,6 +1,4 @@
 #define ASSEMBLY 1
-#define MAXIMUM_CONSOLE_LOGLEVEL 9
-#define DEFAULT_CONSOLE_LOGLEVEL 9
 
 #include <stdint.h>
 #include <device/pci_def.h>
@@ -19,23 +17,32 @@
 #include "cpu/p6/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "debug.c"
+#include "northbridge/amd/amdk8/cpu_rev.c"
 
 #define SIO_BASE 0x2e
 
 static void memreset_setup(void)
 {
-	/* Set the memreset low */
-	outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
-	/* Ensure the BIOS has control of the memory lines */
-	outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
+	if (is_cpu_pre_c0()) {
+		/* Set the memreset low */
+		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
+		/* Ensure the BIOS has control of the memory lines */
+		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
+	}
+	else {
+		/* Ensure the CPU has controll of the memory lines */
+		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
+	}
 }
 
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
-	udelay(800);
-	/* Set memreset_high */
-	outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
-	udelay(90);
+	if (is_cpu_pre_c0()) {
+		udelay(800);
+		/* Set memreset_high */
+		outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
+		udelay(90);
+	}
 }
 
 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
@@ -92,9 +99,6 @@ static void coherent_ht_mainboard(unsigned cpus)
 {
 }
 
-#include "northbridge/amd/amdk8/cpu_ldtstop.c"
-#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
-
 #include "northbridge/amd/amdk8/raminit.c"
 
 #define CONNECTION_0_1 DOWN
@@ -209,7 +213,7 @@ static void main(void)
 	memreset_setup();
 	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 
-#if 1
+#if 0
 	dump_pci_devices();
 #endif
 #if 0
@@ -227,8 +231,21 @@ static void main(void)
 #endif
 #if 0
 	ram_check(0x00000000, msr.lo);
-#else
-	/* Check 16MB of memory @ 0*/
-	ram_check(0x00000000, 0x01000);
+#endif
+#if 0
+	static const struct {
+		unsigned long lo, hi;
+	} check_addrs[] = {
+		/* Check 16MB of memory @ 0*/
+		{ 0x00000000, 0x01000000 },
+#if TOTAL_CPUS > 1
+		/* Check 16MB of memory @ 2GB */
+		{ 0x80000000, 0x81000000 },
+#endif
+	};
+	int i;
+	for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
+		ram_check(check_addrs[i].lo, check_addrs[i].hi);
+	}
 #endif
 }
diff --git a/src/mainboard/newisys/khepri/failover.c b/src/mainboard/newisys/khepri/failover.c
index 8eeeaef7e1..bd9c17020e 100644
--- a/src/mainboard/newisys/khepri/failover.c
+++ b/src/mainboard/newisys/khepri/failover.c
@@ -27,6 +27,10 @@ static void main(void)
 			asm("jmp __cpu_reset");
 		}
 	}
+	/* Is this a deliberate reset by the bios */
+	else if (bios_reset_detected() && last_boot_normal()) {
+		asm("jmp __normal_image");
+	}
 	/* Is this a secondary cpu? */
 	else if (!boot_cpu() && last_boot_normal()) {
 		asm("jmp __normal_image");
diff --git a/src/mainboard/newisys/khepri/irq_tables.c b/src/mainboard/newisys/khepri/irq_tables.c
index 5e4437ca11..142864fbb1 100644
--- a/src/mainboard/newisys/khepri/irq_tables.c
+++ b/src/mainboard/newisys/khepri/irq_tables.c
@@ -1,43 +1,34 @@
-/* This file was generated by getpir.c, do not modify! 
-   (but if you do, please run checkpir on it to verify)
-   Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
-
-   Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
-*/
-
 #include <arch/pirq_routing.h>
 
-
 const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_SIGNATURE, /* u32 signature */
 	PIRQ_VERSION,   /* u16 version   */
-	32+16*18,        /* there can be total 18 devices on the bus */
-	0,           /* Where the interrupt router lies (bus) */
-	0x23,           /* Where the interrupt router lies (dev) */
-	0,         /* IRQs devoted exclusively to PCI usage */
+	32+16*9,        /* there can be total 9 devices on the bus */
+	1,              /* Where the interrupt router lies (bus) */
+	(4<<3)|3,       /* Where the interrupt router lies (dev) */
+	0x0,            /* IRQs devoted exclusively to PCI usage */
 	0x1022,         /* Vendor */
 	0x746b,         /* Device */
-	0,         /* Crap (miniport) */
+	0,              /* Crap (miniport) */
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0x35,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
-	{
-		{0,0xc0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
-		{0,0x50, {{0x1, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
-		{0x2,0x8, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x3, 0},
-		{0x2,0x10, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
-		{0x1,0x18, {{0x4, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0x0, 0},
-		{0x1,0x20, {{0x4, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0x0, 0},
-		{0x2,0x28, {{0x2, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0xa, 0},
-		{0,0x58, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
-		{0x3,0x8, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x1, 0},
-		{0x3,0x10, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x2, 0},
-		{0x3,0x18, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x9, 0},
-		{0,0x30, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
-		{0x1,0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
-		{0x1,0x28, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x5, 0},
-		{0x1,0x20, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x6, 0},
-		{0x1,0x30, {{0x3, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0xb, 0},
-		{0,0x38, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
-		{0,0xc8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
+	0xb0,           /*  u8 checksum , mod 256 checksum must give zero */
+	{	/* bus, devfn,     {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu  */
+		/* PCI Slot 1 */
+		{0x03, (0x01<<3)|0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x01, 0},
+		/* PCI Slot 2 */
+		{0x03, (0x02<<3)|0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}}, 0x02, 0},
+		/* PCI Slot 3 */
+		{0x02, (0x01<<3)|0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x03, 0},
+		/* PCI Slot 4 */
+		{0x02, (0x02<<3)|0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}}, 0x04, 0},
+		/* PCI Slot 5 */
+		{0x04, (0x05<<3)|0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x05, 0},
+		/* PCI Slot 6 */
+		{0x04, (0x04<<3)|0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}}, 0x06, 0},
+		/* Onboard NICS */
+		{0x02, (0x03<<3)|0, {{0x04, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0},
+		{0x02, (0x04<<3)|0, {{0x04, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0},
+		/* Let Linux know about bus 1 */
+		{0x01, (0x04<<3)|3, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0},
 	}
 };
diff --git a/src/mainboard/newisys/khepri/mainboard.c b/src/mainboard/newisys/khepri/mainboard.c
index 88c5977cbb..5e58ebcd18 100644
--- a/src/mainboard/newisys/khepri/mainboard.c
+++ b/src/mainboard/newisys/khepri/mainboard.c
@@ -6,6 +6,7 @@
 
 #include <arch/io.h>
 #include <device/chip.h>
+#include "../../../northbridge/amd/amdk8/northbridge.h"
 #include "chip.h"
 
 
@@ -14,22 +15,27 @@ unsigned long initial_apicid[CONFIG_MAX_CPUS] =
 	0, 1,
 };
 
-static void
-enable(struct chip *chip, enum chip_pass pass)
-{
-
-        struct mainboard_newisys_khepri_config *conf =
-                (struct mainboard_newisys_khepri_config *)chip->chip_info;
-
-        switch (pass) {
-	default: break;
-	case CONF_PASS_PRE_BOOT:
-		break;
-        }
+static struct device_operations mainboard_operations = {
+	.read_resources   = root_dev_read_resources,
+	.set_resources    = root_dev_set_resources,
+	.enable_resources = enable_childrens_resources,
+	.init             = 0,
+	.scan_bus         = amdk8_scan_root_bus,
+	.enable           = 0,
+};
 
+static void enumerate(struct chip *chip)
+{
+	struct chip *child;
+	dev_root.ops = &mainboard_operations;
+	chip->dev = &dev_root;
+	chip->bus = 0;
+	for(child = chip->children; child; child = child->next) {
+		child->bus = &dev_root.link[0];
+	}
 }
 struct chip_control mainboard_newisys_khepri_control = {
-                enable: enable,
-                name:   "Newisys Khepri mainboard "
+	.enumerate = enumerate, 
+	.name      = "Newisys Khepri mainboard ",
 };
 
diff --git a/src/mainboard/newisys/khepri/mptable.c b/src/mainboard/newisys/khepri/mptable.c
index ba8692c1f5..314a04160b 100644
--- a/src/mainboard/newisys/khepri/mptable.c
+++ b/src/mainboard/newisys/khepri/mptable.c
@@ -36,42 +36,42 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
 	smp_write_processors(mc, processor_map);
 
 	{
-		struct pci_dev *dev;
-		uint32_t base;
+		device_t dev;
+
 		/* 8111 */
-		dev = dev_find_slot(0, PCI_DEVFN(0x03,0));
+		dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
 		if (dev) {
 			bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
 			bus_isa	   = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
 			bus_isa++;
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 0:03.0, using defaults\n");
+			printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
 
-			bus_8111_1 = 3;
-			bus_isa = 4;
+			bus_8111_1 = 4;
+			bus_isa = 5;
 		}
 		/* 8131-1 */
-		dev = dev_find_slot(0, PCI_DEVFN(0x01,0));
+		dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
 		if (dev) {
 			bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 0:01.0, using defaults\n");
+			printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
 
-			bus_8131_1 = 1;
+			bus_8131_1 = 2;
 		}
 		/* 8131-2 */
-		dev = dev_find_slot(0, PCI_DEVFN(0x02,0));
+		dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
 		if (dev) {
 			bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
 
 		}
 		else {
-			printk_debug("ERROR - could not find PCI 0:02.0, using defaults\n");
+			printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
 
-			bus_8131_2 = 2;
+			bus_8131_2 = 3;
 		}
 	}
 
@@ -85,17 +85,17 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
 
 	smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
 	{
-		struct pci_dev *dev;
+		device_t dev;
 		uint32_t base;
 		/* 8131 apic 3 */
-		dev = dev_find_slot(0, PCI_DEVFN(0x01,1));
+		dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
 		if (dev) {
 			base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
 			base &= PCI_BASE_ADDRESS_MEM_MASK;
 			smp_write_ioapic(mc, 0x03, 0x11, base);
 		}
 		/* 8131 apic 4 */
-		dev = dev_find_slot(0, PCI_DEVFN(0x02,1));
+		dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
 		if (dev) {
 			base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
 			base &= PCI_BASE_ADDRESS_MEM_MASK;
@@ -144,10 +144,6 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
 		bus_isa, 0x00, MP_APIC_ALL, 0x01);
 
 
-	/* AGP Slot */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		0x03, (6<<2)|0, 0x02, 0x12);
-
 	/* PCI Slot 1 */
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
 		bus_8131_2, (1<<2)|0, 0x02, 0x11);