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| author | Stefan Reinauer <stepan@coresystems.de> | 2010-03-29 22:08:01 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-03-29 22:08:01 +0000 |
| commit | 798ef2893c44ce3194c539c8c5db33d11e8edbac (patch) | |
| tree | 405318f804b41070e16ca6b907d65a1e27cc5071 /src/mainboard/newisys/khepri | |
| parent | 72bdfeb6987f9578ac7fee3f21140ab5853d6179 (diff) | |
| download | coreboot-798ef2893c44ce3194c539c8c5db33d11e8edbac.tar.xz | |
This drops the ASSEMBLY define from romstage.c, too
(since it's not assembly code, this was a dirty hack anyways)
Also run
awk 1 RS= ORS="\n\n" < $FILE > $FILE.nonewlines
mv $FILE.nonewlines $FILE
on romstage.c because my perl -pi -e 's,#define ASSEMBLY 1,,g' */*/romstage.c
cut some holes into the source.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/newisys/khepri')
| -rw-r--r-- | src/mainboard/newisys/khepri/romstage.c | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c index 65af0ae1e5..7ee9d1600a 100644 --- a/src/mainboard/newisys/khepri/romstage.c +++ b/src/mainboard/newisys/khepri/romstage.c @@ -3,7 +3,6 @@ * Adapted by Stefan Reinauer <stepan@coresystems.de> * Additional (C) 2007 coresystems GmbH */ -#define ASSEMBLY 1 #include <stdint.h> @@ -100,14 +99,12 @@ static inline int spd_read_byte(unsigned device, unsigned address) #endif #include "cpu/amd/dualcore/dualcore.c" - #include "cpu/amd/car/copy_and_run.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -175,7 +172,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) soft_reset(); } - allow_all_aps_stop(bsp_apicid); nodes = get_nodes(); @@ -194,3 +190,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + |