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| author | Paul Menzel <paulepanter@users.sourceforge.net> | 2014-02-02 22:05:48 +0100 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-02-12 02:27:07 +0100 |
| commit | 4549e5a6650b4d4634a46285796e63e31c99f9c8 (patch) | |
| tree | d3917a209e28bf51a4d64de113b07d90f6b3012f /src/mainboard/nvidia/l1_2pvv | |
| parent | 090883932386b12fdfb85148041f551be4596f4f (diff) | |
| download | coreboot-4549e5a6650b4d4634a46285796e63e31c99f9c8.tar.xz | |
AMD K8 boards’ `romstage.c`: Spell sync*hr*onize correctly
Change-Id: I92e6e7f1292f66642aa0336064a4eccba104dd08
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5101
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/nvidia/l1_2pvv')
| -rw-r--r-- | src/mainboard/nvidia/l1_2pvv/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index 785b52f969..ab0f1dd8ad 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -167,7 +167,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - init_timer(); /* Need to use TMICT to synconize FID/VID. */ + init_timer(); /* Need to use TMICT to synchronize FID/VID. */ needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); |