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authorPatrick Georgi <patrick.georgi@coresystems.de>2009-11-27 16:55:13 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2009-11-27 16:55:13 +0000
commit436f99b72a75e38c4a1558a23642ea838e621745 (patch)
tree2030053c23283ddee57d7019d364e408cbb278d9 /src/mainboard/nvidia/l1_2pvv
parentc58290c2ff3a77ebca00d9d2edbe005d6e950e0f (diff)
downloadcoreboot-436f99b72a75e38c4a1558a23642ea838e621745.tar.xz
Eliminate special case id.inc/id.lds in favor of a configuration variable ID_SECTION_OFFSET
which is normally set to 0x10 (the current default) and set to 0x80 (the current alternative) where necessary (if romstraps get in the way). For Kconfig, the special case is set per southbridge (as these define the necessity for this workaround), for newconfig it's added to each single board. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/nvidia/l1_2pvv')
-rw-r--r--src/mainboard/nvidia/l1_2pvv/Config.lb4
-rw-r--r--src/mainboard/nvidia/l1_2pvv/Makefile.inc4
-rw-r--r--src/mainboard/nvidia/l1_2pvv/Options.lb4
3 files changed, 8 insertions, 4 deletions
diff --git a/src/mainboard/nvidia/l1_2pvv/Config.lb b/src/mainboard/nvidia/l1_2pvv/Config.lb
index 0b1bfb0ac1..ba30037815 100644
--- a/src/mainboard/nvidia/l1_2pvv/Config.lb
+++ b/src/mainboard/nvidia/l1_2pvv/Config.lb
@@ -141,8 +141,8 @@ end
##
## Include an id string (For safe flashing)
##
-mainboardinit southbridge/nvidia/mcp55/id.inc
-ldscript /southbridge/nvidia/mcp55/id.lds
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
##
## ROMSTRAP table for MCP55
diff --git a/src/mainboard/nvidia/l1_2pvv/Makefile.inc b/src/mainboard/nvidia/l1_2pvv/Makefile.inc
index 66cc3e6cb0..ccb1094a0e 100644
--- a/src/mainboard/nvidia/l1_2pvv/Makefile.inc
+++ b/src/mainboard/nvidia/l1_2pvv/Makefile.inc
@@ -33,7 +33,7 @@ initobj-y += crt0.o
crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
crt0-y += auto.inc
@@ -41,7 +41,7 @@ crt0-y += auto.inc
ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
ldscript-y += ../../../../src/arch/i386/lib/failover.lds
ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
diff --git a/src/mainboard/nvidia/l1_2pvv/Options.lb b/src/mainboard/nvidia/l1_2pvv/Options.lb
index b7b445af36..00efb92b09 100644
--- a/src/mainboard/nvidia/l1_2pvv/Options.lb
+++ b/src/mainboard/nvidia/l1_2pvv/Options.lb
@@ -113,6 +113,8 @@ uses CONFIG_WAIT_BEFORE_CPUS_INIT
uses CONFIG_USE_PRINTK_IN_CAR
+uses CONFIG_ID_SECTION_OFFSET
+
###
### Build options
###
@@ -345,5 +347,7 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
## Select power on after power fail setting
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_ID_SECTION_OFFSET=0x80
+
### End Options.lb
end