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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-09-19 09:47:16 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-09-20 21:55:12 +0200 |
| commit | a5aad2ed68690d748c650f69a2e39f91a7b02608 (patch) | |
| tree | 7ad419bc13bcf13e546481558aa1a4c923821c07 /src/mainboard/nvidia | |
| parent | 531b87ac4e8038aedf9c44c29fe2c1fc31adb346 (diff) | |
| download | coreboot-a5aad2ed68690d748c650f69a2e39f91a7b02608.tar.xz | |
src/mainboard/lenovo-winent: Add space around operators
Change-Id: Iab2a879ebdea9d93ef5eb7e3abf875036c1e1cb4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16641
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/nvidia')
| -rw-r--r-- | src/mainboard/nvidia/l1_2pvv/mptable.c | 4 | ||||
| -rw-r--r-- | src/mainboard/nvidia/l1_2pvv/romstage.c | 8 |
2 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/nvidia/l1_2pvv/mptable.c b/src/mainboard/nvidia/l1_2pvv/mptable.c index d000b1a4e7..76bb73cafa 100644 --- a/src/mainboard/nvidia/l1_2pvv/mptable.c +++ b/src/mainboard/nvidia/l1_2pvv/mptable.c @@ -58,8 +58,8 @@ static void *smp_write_config_table(void *v) /* Initialize interrupt mapping*/ dword = pci_read_config32(dev, 0x74); - dword &= ~(1<<15); - dword |= 1<<2; + dword &= ~(1 << 15); + dword |= 1 << 2; pci_write_config32(dev, 0x74, dword); dword = 0x43c6c643; diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index cfe5bebffa..d0966ee4fe 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -81,11 +81,11 @@ static void sio_setup(void) pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); - dword |= (1<<0); + dword |= (1 << 0); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); - dword |= (1<<16); + dword |= (1 << 16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); } @@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); } enable_fid_change(); @@ -158,7 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // show final fid and vid { msr_t msr; - msr=rdmsr(0xc0010042); + msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); } #endif |