newconfig is no more.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 0 insertions, 726 deletions

diff --git a/src/mainboard/nvidia/l1_2pvv/Config.lb b/src/mainboard/nvidia/l1_2pvv/Config.lb
deleted file mode 100644
index ba30037815..0000000000
--- a/src/mainboard/nvidia/l1_2pvv/Config.lb
+++ /dev/null
@@ -1,373 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/failovercalculation.lb
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-#needed by irq_tables and mptable and acpi_tables
-object get_bus_conf.o
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-if CONFIG_GENERATE_ACPI_TABLES
-	object acpi_tables.o
-	object fadt.o
-	makerule dsdt.c
-		depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
-		action  "/usr/sbin/iasl -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
-		action  "mv dsdt_lb.hex dsdt.c"
-	end
-	object ./dsdt.o
-
-	#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
-
-	if CONFIG_ACPI_SSDTX_NUM
-	    makerule ssdt6.c
-			depends "$(CONFIG_MAINBOARD)/dx/pci6.asl"
-			action  "/usr/sbin/iasl -tc $(CONFIG_MAINBOARD)/dx/pci6.asl"
-			action  "perl -pi -e 's/AmlCode/AmlCode_ssdt6/g' pci6.hex"
-			action  "mv pci6.hex ssdt6.c"
-	    end
-	    object ./ssdt6.o
-	    makerule ssdt5.c
-			depends "$(CONFIG_MAINBOARD)/dx/pci5.asl"
-			action  "/usr/sbin/iasl -tc $(CONFIG_MAINBOARD)/dx/pci5.asl"
-			action  "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
-			action  "mv pci5.hex ssdt5.c"
-	    end
-	    object ./ssdt5.o
-	end
-end
-
-	if CONFIG_USE_INIT
-		makerule ./cache_as_ram_auto.o
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-	else
-		makerule ./cache_as_ram_auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-	end
-
-if CONFIG_USE_FAILOVER_IMAGE
-else
-    if CONFIG_AP_CODE_IN_CAR
-	makerule ./apc_auto.o
-		depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
-		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
-	end
-	ldscript /arch/i386/init/ldscript_apc.lb
-    end
-end
-
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-	if CONFIG_USE_INIT
-		ldscript /cpu/x86/32bit/entry32.lds
-	end
-
-	if CONFIG_USE_INIT
-		ldscript /cpu/amd/car/cache_as_ram.lds
-	end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-    end
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## ROMSTRAP table for MCP55
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
-	ldscript /southbridge/nvidia/mcp55/romstrap.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
-	ldscript /southbridge/nvidia/mcp55/romstrap.lds
-    end
-end
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-		ldscript /arch/i386/lib/failover_failover.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-		ldscript /arch/i386/lib/failover.lds
-    end
-end
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject cache_as_ram_auto.o
-	else
-		mainboardinit ./cache_as_ram_auto.inc
-	end
-
-##
-## Include the secondary Configuration files
-##
-config chip.h
-
-chip northbridge/amd/amdk8/root_complex
-	device apic_cluster 0 on
-		chip cpu/amd/socket_F
-			device apic 0 on end
-		end
-	end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8 #mc0
-			device pci 18.0 on
-				#  devices on link 0, link 0 == LDT 0
-				chip southbridge/nvidia/mcp55
-					device pci 0.0 on end   # HT
-					device pci 1.0 on # LPC
-						chip superio/winbond/w83627ehg
-							device pnp 2e.0 off #  Floppy
-					 			io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
-							end
-							device pnp 2e.1 off #  Parallel Port
-					 			io 0x60 = 0x378
-								irq 0x70 = 7
-							end
-							device pnp 2e.2 on #  Com1
-					 			io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp 2e.3 off #  Com2
-					 			io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-							device pnp 2e.5 on #  Keyboard
-					 			io 0x60 = 0x60
-					 			io 0x62 = 0x64
-								irq 0x70 = 1
-								irq 0x72 = 12
-							end
-							device pnp 2e.6 off  # SFI
-					 			io 0x62 = 0x100
-							end
-							device pnp 2e.7 off #  GPIO_GAME_MIDI
-								io 0x60 = 0x220
-								io 0x62 = 0x300
-								irq 0x70 = 9
-							end
-							device pnp 2e.8 off end #  WDTO_PLED
-							device pnp 2e.9 off end #  GPIO_SUSLED
-							device pnp 2e.a off end #  ACPI
-							device pnp 2e.b on #  HW Monitor
- 					 			io 0x60 = 0x290
-								irq 0x70 = 5
-							end
-						end
-					end
-					device pci 1.1 on # SM 0
-						chip drivers/generic/generic #dimm 0-0-0
-							device i2c 50 on end
-						end
-						chip drivers/generic/generic #dimm 0-0-1
-							device i2c 51 on end
-						end
-						chip drivers/generic/generic #dimm 0-1-0
-							device i2c 52 on end
-						end
-						chip drivers/generic/generic #dimm 0-1-1
-							device i2c 53 on end
-						end
-						chip drivers/generic/generic #dimm 1-0-0
-							device i2c 54 on end
-						end
-						chip drivers/generic/generic #dimm 1-0-1
-							device i2c 55 on end
-						end
-						chip drivers/generic/generic #dimm 1-1-0
-							device i2c 56 on end
-						end
-						chip drivers/generic/generic #dimm 1-1-1
-							device i2c 57 on end
-						end
-					end # SM
-					device pci 1.1 on # SM 1
-#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
-#						chip drivers/generic/generic #PCIXA Slot1
-#							device i2c 50 on end
-#						end
-#						chip drivers/generic/generic #PCIXB Slot1
-#							device i2c 51 on end
-#						end
-#						chip drivers/generic/generic #PCIXB Slot2
-#							device i2c 52 on end
-#						end
-#						chip drivers/generic/generic #PCI Slot1
-#							device i2c 53 on end
-#						end
-#						chip drivers/generic/generic #Master MCP55 PCI-E
-#							device i2c 54 on end
-#						end
-#						chip drivers/generic/generic #Slave MCP55 PCI-E
-#							device i2c 55 on end
-#						end
-						chip drivers/generic/generic #MAC EEPROM
-							device i2c 51 on end
-						end
-
-					end # SM
-					device pci 2.0 on end # USB 1.1
-					device pci 2.1 on end # USB 2
-					device pci 4.0 on end # IDE
-					device pci 5.0 on end # SATA 0
-					device pci 5.1 on end # SATA 1
-					device pci 5.2 on end # SATA 2
-					device pci 6.0 on end # PCI
-					device pci 6.1 on end # AZA
-					device pci 8.0 on end # NIC
-					device pci 9.0 on end # NIC
-		       			device pci a.0 on end # PCI E 5
-		       			device pci b.0 off end # PCI E 4
-					device pci c.0 off end # PCI E 3
-					device pci d.0 on end # PCI E 2
-					device pci e.0 off end # PCI E 1
-		       			device pci f.0 on end # PCI E 0
-					register "ide0_enable" = "1"
-					register "sata0_enable" = "1"
-					register "sata1_enable" = "1"
-					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
-					register "mac_eeprom_addr" = "0x51"
-				end
-			end #  device pci 18.0
-			device pci 18.0 on end # Link 1
-			device pci 18.0 on
-				#  devices on link 2, link 2 == LDT 2
-				chip southbridge/nvidia/mcp55
-					device pci 0.0 on end   # HT
-					device pci 1.0 on end  # LPC
-					device pci 1.1 on end # SM 0
-					device pci 2.0 off end # USB 1.1
-					device pci 2.1 off end # USB 2
-					device pci 4.0 off end # IDE
-					device pci 5.0 on end # SATA 0
-					device pci 5.1 on end # SATA 1
-					device pci 5.2 on end # SATA 2
-					device pci 6.0 off end # PCI
-					device pci 6.1 off end # AZA
-					device pci 8.0 on end # NIC
-					device pci 9.0 on end # NIC
-		       			device pci a.0 on end # PCI E 5
-		       			device pci b.0 off end # PCI E 4
-					device pci c.0 off end # PCI E 3
-					device pci d.0 on end # PCI E 2
-					device pci e.0 on end # PCI E 1
-		       			device pci f.0 on end # PCI E 0
-					register "ide0_enable" = "1"
-					register "sata0_enable" = "1"
-					register "sata1_enable" = "1"
-					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
-					register "mac_eeprom_addr" = "0x51"
-				end
-			end # device pci 18.0
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end # mc0
-
-	end # PCI domain
-
-#       chip drivers/generic/debug
-#		device pnp 0.0 off end # chip name
-#		device pnp 0.1 on end # pci_regs_all
-#		device pnp 0.2 on end # mem
-#		device pnp 0.3 off end # cpuid
-#		device pnp 0.4 on end # smbus_regs_all
-#		device pnp 0.5 off end # dual core msr
-#		device pnp 0.6 off end # cache size
-#		device pnp 0.7 off end # tsc
-#		device pnp 0.8 off  end # io
-#		device pnp 0.9 off end # io
-#       end
-end #root_complex
diff --git a/src/mainboard/nvidia/l1_2pvv/Options.lb b/src/mainboard/nvidia/l1_2pvv/Options.lb
deleted file mode 100644
index 00efb92b09..0000000000
--- a/src/mainboard/nvidia/l1_2pvv/Options.lb
+++ /dev/null
@@ -1,353 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_ACPI_SSDTX_NUM
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_FAILOVER_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_FAILOVER_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_USBDEBUG_DIRECT
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_SERIAL_CPU_INIT
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-uses CONFIG_PCI_64BIT_PREF_MEM
-
-uses CONFIG_RAMTOP
-
-uses CONFIG_AP_CODE_IN_CAR
-
-uses CONFIG_MEM_TRAIN_SEQ
-
-uses CONFIG_WAIT_BEFORE_CPUS_INIT
-
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_ID_SECTION_OFFSET
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-#default CONFIG_ROM_SIZE=0x100000
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-
-#FALLBACK: 256K-4K
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-#FAILOVER: 4K
-default CONFIG_FAILOVER_SIZE=0x01000
-
-#more 1M for pgtbl
-default CONFIG_RAMTOP=2048*1024
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-default CONFIG_HAVE_FAILOVER_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-## ACPI tables will be included
-default CONFIG_GENERATE_ACPI_TABLES=0
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-
-#default CONFIG_SERIAL_CPU_INIT=0
-
-default CONFIG_ENABLE_APIC_EXT_ID=0
-default CONFIG_APIC_ID_OFFSET=0x10
-default CONFIG_LIFT_BSP_APIC_ID=1
-
-#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
-#2G
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
-#1G
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-#512M
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
-
-#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
-
-#Opteron K8 1G HT Support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-#default CONFIG_USBDEBUG_DIRECT=1
-
-#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
-default CONFIG_HT_CHAIN_UNITID_BASE=0
-
-#real SB Unit ID, default is 0x20, mean dont touch it at last
-#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
-
-#make the SB HT chain on bus 0, default is not (0)
-default CONFIG_SB_HT_CHAIN_ON_BUS0=2
-
-#only offset for SB chain?, default is yes(1)
-default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#allow capable device use that above 4G
-#default CONFIG_PCI_64BIT_PREF_MEM=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc8000
-default CONFIG_DCACHE_RAM_SIZE=0x08000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
-
-default CONFIG_AP_CODE_IN_CAR=0
-default CONFIG_MEM_TRAIN_SEQ=1
-default CONFIG_WAIT_BEFORE_CPUS_INIT=1
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="l1_2pvv"
-default CONFIG_MAINBOARD_VENDOR="NVIDIA"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00100000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-#default CONFIG_COMPRESSED_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_ID_SECTION_OFFSET=0x80
-
-### End Options.lb
-end