diff options
| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-25 09:03:55 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-25 09:03:55 +0000 |
| commit | df323fcefd6020f8f418a13d65a075d282eed3de (patch) | |
| tree | 1a7180ff77784fca47bb25785aad7a8b7db9dadb /src/mainboard/nvidia | |
| parent | 48ae6086da64eb260c6eed676c593cdcd0957fbf (diff) | |
| download | coreboot-df323fcefd6020f8f418a13d65a075d282eed3de.tar.xz | |
MCP55: Add TINY_BOOTBLOCK support.
Also, move CONFIG_HT_CHAIN_END_UNITID_BASE #ifdef block to mcp55.h to make
the build work (but this is a good idea anyway, as it's used in
multiple files).
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6123 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/nvidia')
| -rw-r--r-- | src/mainboard/nvidia/l1_2pvv/romstage.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index 69f3eb1fe9..8e4067f1f0 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -82,7 +82,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) @@ -124,7 +123,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); - mcp55_enable_rom(); } if (bist == 0) |