summaryrefslogtreecommitdiff
path: root/src/mainboard/nvidia
diff options
context:
space:
mode:
authorPatrick Georgi <patrick.georgi@coresystems.de>2010-03-18 20:58:41 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2010-03-18 20:58:41 +0000
commit78acf932912669eb0eb7f7280da1b3c550035ebb (patch)
tree89f13a87df362395527d41f42d0a57a167eab8db /src/mainboard/nvidia
parent2bd91003413d431f0a4db6c3c6691f4b688cf5c5 (diff)
downloadcoreboot-78acf932912669eb0eb7f7280da1b3c550035ebb.tar.xz
Remove remaining uses of
HAVE_FAILOVER_BOOT HAVE_FALLBACK_BOOT USE_FAILOVER_IMAGE USE_FALLBACK_IMAGE Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5259 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/nvidia')
-rw-r--r--src/mainboard/nvidia/l1_2pvv/Kconfig10
-rw-r--r--src/mainboard/nvidia/l1_2pvv/romstage.c10
2 files changed, 0 insertions, 20 deletions
diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig
index e12f0274f9..0db62a4c8f 100644
--- a/src/mainboard/nvidia/l1_2pvv/Kconfig
+++ b/src/mainboard/nvidia/l1_2pvv/Kconfig
@@ -76,16 +76,6 @@ config PCI_64BIT_PREF_MEM
default n
depends on BOARD_NVIDIA_L1_2PVV
-config HAVE_FALLBACK_BOOT
- bool
- default n
- depends on BOARD_NVIDIA_L1_2PVV
-
-config USE_FALLBACK_IMAGE
- bool
- default n
- depends on BOARD_NVIDIA_L1_2PVV
-
config HW_MEM_HOLE_SIZEK
hex
default 0x100000
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index 3e8f9e7ee3..ad04b5eeb3 100644
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -54,7 +54,6 @@
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
-#if CONFIG_USE_FAILOVER_IMAGE==0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#if CONFIG_USBDEBUG_DIRECT
@@ -70,15 +69,11 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
#include "superio/winbond/w83627ehg/w83627ehg_early_init.c"
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
@@ -148,8 +143,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/fidvid.c"
-#endif
-
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@@ -175,7 +168,6 @@ static void sio_setup(void)
}
-#if CONFIG_USE_FAILOVER_IMAGE==0
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
@@ -301,5 +293,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
-
-#endif