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authorPatrick Georgi <patrick.georgi@coresystems.de>2010-10-05 17:59:12 +0000
committerMyles Watson <mylesgw@gmail.com>2010-10-05 17:59:12 +0000
commitabc0c7791e18dbd97949a49016f9ebedb823ed84 (patch)
treea8c014275fe0c920ccf47f929ec7fe6a151834ea /src/mainboard/nvidia
parent5692c5733633bfb8b23f1111de152eff0233b713 (diff)
downloadcoreboot-abc0c7791e18dbd97949a49016f9ebedb823ed84.tar.xz
attached patch moves a couple more config flags out of romstage:
CK804_USE_NIC, CK804_USE_ACI, CK804_NUM. MCP55_USE_NIC, MCP55_USE_ACI, MCP55_NUM. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> Acked-by: Pter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5912 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/nvidia')
-rw-r--r--src/mainboard/nvidia/l1_2pvv/Kconfig6
-rw-r--r--src/mainboard/nvidia/l1_2pvv/romstage.c4
2 files changed, 6 insertions, 4 deletions
diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig
index 1a260bf8e0..06e10ab92a 100644
--- a/src/mainboard/nvidia/l1_2pvv/Kconfig
+++ b/src/mainboard/nvidia/l1_2pvv/Kconfig
@@ -9,6 +9,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_AMD_AMDK8
select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
select SOUTHBRIDGE_NVIDIA_MCP55
+ select MCP55_USE_NIC
+ select MCP55_USE_AZA
select SUPERIO_WINBOND_W83627EHG
select HAVE_OPTION_TABLE
select HAVE_BUS_CONFIG
@@ -44,6 +46,10 @@ config MEM_TRAIN_SEQ
int
default 1
+config MCP55_NUM
+ int
+ default 2
+
config SB_HT_CHAIN_ON_BUS0
int
default 2
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index dc76e0a32e..fc135d8378 100644
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -100,10 +100,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/dualcore/dualcore.c"
-#define MCP55_NUM 2
-#define MCP55_USE_NIC 1
-#define MCP55_USE_AZA 1
-
#define MCP55_PCI_E_X_0 2
#define MCP55_PCI_E_X_1 4