More boards in kconfig, and moved -O2 flag for romcc into

ROMCCFLAGS, so boards can override it where necessary.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4730 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 215 insertions, 1 deletions

diff --git a/src/mainboard/nvidia/Kconfig b/src/mainboard/nvidia/Kconfig
index 792d600548..54a0c0a99c 100644
--- a/src/mainboard/nvidia/Kconfig
+++ b/src/mainboard/nvidia/Kconfig
@@ -1 +1,8 @@
-#
+choice
+	prompt "Mainboard model"
+	depends on VENDOR_NVIDIA
+        
+source "src/mainboard/nvidia/l1_2pvv/Kconfig"
+
+endchoice
+
diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig
new file mode 100644
index 0000000000..a153993f09
--- /dev/null
+++ b/src/mainboard/nvidia/l1_2pvv/Kconfig
@@ -0,0 +1,148 @@
+config BOARD_NVIDIA_L1_2PVV
+	bool "L1 2PVV"
+	select ARCH_X86
+	select CPU_AMD_K8
+	select CPU_AMD_SOCKET_F
+	select NORTHBRIDGE_AMD_AMDK8
+	select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
+	select SOUTHBRIDGE_NVIDIA_MCP55
+	select SUPERIO_WINBOND_W83627EHG
+	select PIRQ_TABLE
+	select USE_PRINTK_IN_CAR
+	select USE_DCACHE_RAM
+	select HAVE_HARD_RESET
+	select HAVE_HIGH_TABLES
+	select IOAPIC
+	select MEM_TRAIN_SEQ
+	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	select K8_REV_F_SUPPORT
+ 
+config MAINBOARD_DIR
+	string
+	default nvidia/l1_2pvv
+	depends on BOARD_NVIDIA_L1_2PVV
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xc8000
+	depends on BOARD_NVIDIA_L1_2PVV
+	
+config DCACHE_RAM_SIZE
+	hex
+	default 0x08000
+	depends on BOARD_NVIDIA_L1_2PVV
+
+config DCACHE_RAM_GLOBAL_VAR_SIZE
+	hex
+	default 0x01000
+	depends on BOARD_NVIDIA_L1_2PVV
+
+config APIC_ID_OFFSET
+	hex	
+	default 16
+	depends on BOARD_NVIDIA_L1_2PVV
+
+config SB_HT_CHAIN_ON_BUS0
+	int
+	default 2
+	depends on BOARD_NVIDIA_L1_2PVV
+
+config LB_CKS_RANGE_START
+	int
+	default 49
+	depends on BOARD_NVIDIA_L1_2PVV
+
+config LB_CKS_RANGE_END
+	int
+	default 122
+	depends on BOARD_NVIDIA_L1_2PVV
+
+config LB_CKS_LOC
+	int
+        default 123
+	depends on BOARD_NVIDIA_L1_2PVV
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "l1_2pvv"
+	depends on BOARD_NVIDIA_L1_2PVV
+
+config PCI_64BIT_PREF_MEM
+	bool
+        default n
+	depends on BOARD_NVIDIA_L1_2PVV
+
+config HAVE_FALLBACK_BOOT
+	bool
+	default n
+	depends on BOARD_NVIDIA_L1_2PVV
+
+config USE_FALLBACK_IMAGE
+	bool
+	default n
+	depends on BOARD_NVIDIA_L1_2PVV
+
+config HW_MEM_HOLE_SIZEK
+	hex
+	default 0x100000
+	depends on BOARD_NVIDIA_L1_2PVV
+
+config MAX_CPUS
+	int
+	default 2
+	depends on BOARD_NVIDIA_L1_2PVV
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 1
+	depends on BOARD_NVIDIA_L1_2PVV
+
+config AP_CODE_IN_CAR
+	bool	
+	default n
+	depends on BOARD_NVIDIA_L1_2PVV
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+	bool	
+	default n
+	depends on BOARD_NVIDIA_L1_2PVV
+
+config HT_CHAIN_UNITID_BASE
+	hex
+	default 0x0
+	depends on BOARD_NVIDIA_L1_2PVV
+
+config HT_CHAIN_END_UNITID_BASE
+	hex	
+	default 0x0
+	depends on BOARD_NVIDIA_L1_2PVV
+
+config USE_INIT
+	bool
+	default n
+	depends on BOARD_NVIDIA_L1_2PVV
+
+config SERIAL_CPU_INIT
+	bool	
+	default n
+	depends on BOARD_NVIDIA_L1_2PVV
+
+config WAIT_BEFORE_CPUS_INIT
+	bool	
+	default n
+	depends on BOARD_NVIDIA_L1_2PVV
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+	hex
+	default 0x1022
+	depends on BOARD_NVIDIA_L1_2PVV
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+	hex
+	default 0x2b80
+	depends on BOARD_NVIDIA_L1_2PVV
+
+config IRQ_SLOT_COUNT
+	int
+	default 11
+	depends on BOARD_NVIDIA_L1_2PVV
diff --git a/src/mainboard/nvidia/l1_2pvv/Makefile.inc b/src/mainboard/nvidia/l1_2pvv/Makefile.inc
new file mode 100644
index 0000000000..56cbf31bf0
--- /dev/null
+++ b/src/mainboard/nvidia/l1_2pvv/Makefile.inc
@@ -0,0 +1,59 @@
+##
+## This file is part of the coreboot project.
+## 
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+driver-y +=  mainboard.o
+
+#needed by irq_tables and mptable and acpi_tables
+obj-y += get_bus_conf.o
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+obj-$(CONFIG_USE_INIT) += cache_as_ram_auto.o
+obj-$(CONFIG_AP_CODE_IN_CAR) += apc_auto.o
+
+# This is part of the conversion to init-obj and away from included code. 
+initobj-y += crt0.o
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc
+crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
+crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds
+ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
+
+ifdef POST_EVALUATION
+
+$(obj)/mainboard/$(MAINBOARDDIR)/apc_auto.o: $(src)/mainboard/$(MAINBOARDDIR)/apc_auto.c $(obj)/option_table.h
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/apc_auto.c -o $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
+	perl -e 's/\.rodata/.rom.data/g' -pi $@
+	perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif