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| author | Jonathan A. Kollasch <jakllsch@kollasch.net> | 2015-07-07 12:57:46 -0500 |
|---|---|---|
| committer | Jonathan A. Kollasch <jakllsch@kollasch.net> | 2015-07-14 13:40:07 +0200 |
| commit | ec505ad21c923c114a16b2710a0113f657765430 (patch) | |
| tree | c3ecdb6021982e2d79220b63d40448bebe43baf2 /src/mainboard/nvidia | |
| parent | fb4233bb22602c3802da39200b85845407e0c496 (diff) | |
| download | coreboot-ec505ad21c923c114a16b2710a0113f657765430.tar.xz | |
azalia: fix up and clean up shrinkage of boilerplate code
Should fix regression in HDA verb setup on nvidia mcp55 and intel sch
southbridges. The mcp55 code could not find the mainboard's verb table
because the table was not even being compiled in. The sch boards appeared
to have the same issue.
Intel broadwell and fsp_bd82x6x seemed to have not gotten the boilerplate
shrink, so apply it to those too.
Followup-to: Ib3e09644c0ee71aacb067adaa85653d151b52078
(azalia: Shrink boilerplate)
Change-Id: If7aae69f5171db67055ffe220bdff392caaa5d9f
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10826
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/nvidia')
| -rw-r--r-- | src/mainboard/nvidia/l1_2pvv/hda_verb.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/mainboard/nvidia/l1_2pvv/hda_verb.c b/src/mainboard/nvidia/l1_2pvv/hda_verb.c index bb20c2bc3c..68076f9dad 100644 --- a/src/mainboard/nvidia/l1_2pvv/hda_verb.c +++ b/src/mainboard/nvidia/l1_2pvv/hda_verb.c @@ -19,7 +19,9 @@ * Foundation, Inc. */ -static u32 mainboard_cim_verb_data[] = { +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { /* coreboot specific header */ 0x10ec0880, // Codec Vendor / Device ID: Realtek ALC880 0x00000000, // Subsystem ID @@ -64,4 +66,7 @@ static u32 mainboard_cim_verb_data[] = { /* NID 0x1f, S/PDIF-IN */ AZALIA_PIN_CFG(0x0, 0x1f, 0x01c59150), }; + +const u32 pc_beep_verbs[0] = {}; + AZALIA_ARRAY_SIZES; |