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| author | Marc Jones <marcjones@sysproconsulting.com> | 2021-01-21 13:23:58 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-26 10:35:04 +0000 |
| commit | 05a480acea84c131469e2baca2aff23e2deddf09 (patch) | |
| tree | cbf36cf3e1c093ec6f194bd94d0ab36db0a98ca2 /src/mainboard/ocp/deltalake/devicetree.cb | |
| parent | 31ed8856f9c6f06b8594f80b4abc39952ee84247 (diff) | |
| download | coreboot-05a480acea84c131469e2baca2aff23e2deddf09.tar.xz | |
ocp/deltalake: Set C-State config
Set the supported C-State to C1 and C6. This matches the states in
CPUID(5).
Change-Id: If32b8256097b5b2bee7fb074fab105e4b54d14b3
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49803
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/ocp/deltalake/devicetree.cb')
| -rw-r--r-- | src/mainboard/ocp/deltalake/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb index 8b6e3aea6c..70dd6d683b 100644 --- a/src/mainboard/ocp/deltalake/devicetree.cb +++ b/src/mainboard/ocp/deltalake/devicetree.cb @@ -46,6 +46,8 @@ chip soc/intel/xeon_sp/cpx .PortLinkSpeed = PcieAuto, }" + register "cstate_states" = "CSTATES_C1C6" + device cpu_cluster 0 on device lapic 0 on end end |