mb/ocp/deltalake: Add OCP Delta Lake mainboard

OCP Delta Lake server is a one socket server platform powered by
Intel Cooper Lake Scalable Processor.

The Delta Lake server is a blade of OCP Yosemite V3 multi-host
sled.

TESTED=Successfully booted on both YV3 config A Delta Lake server
and config C Delta Lake server. The coreboot payload is Linux kernel
plus u-root as initramfs. Below are the logs of ssh'ing into a
config C deltalake server:
jonzhang@devvm2573:~$ ssh yv3-cth
root@ip's password:
Last login: Mon Apr 20 21:56:51 2020 from
[root@dhcp-100-96-192-156 ~]# lscpu
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                52
On-line CPU(s) list:   0-51
...
[root@dhcp-100-96-192-156 ~]# cbmem
34 entries total:

   0:1st timestamp                                     28,621,996
  40:device configuration                              178,835,602 (150,213,605)
...
Total Time: 135,276,123,874,479,544
[root@dhcp-100-96-192-156 ~]# cat /proc/cmdline
root=UUID=f0fc52f2-e8b8-40f8-ac42-84c9f838394c ro crashkernel=auto selinux=0 console=ttyS1,57600n1 LANG=en_US.UTF-8 earlyprintk=serial,ttyS0,57600 earlyprintk=uart8250,io,0x2f8,57600n1 console=ttyS0,57600n1 loglevel=7 systemd.log_level=debug

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I0a5234d483e4ddea1cd37643b41f6aba65729c8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>

1 files changed, 80 insertions, 0 deletions

diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb
new file mode 100644
index 0000000000..26912d113d
--- /dev/null
+++ b/src/mainboard/ocp/deltalake/devicetree.cb
@@ -0,0 +1,80 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip soc/intel/xeon_sp/cpx
+
+	register "pirqa_routing" = "PCH_IRQ11"
+	register "pirqb_routing" = "PCH_IRQ10"
+	register "pirqc_routing" = "PCH_IRQ11"
+	register "pirqd_routing" = "PCH_IRQ11"
+	register "pirqe_routing" = "PCH_IRQ11"
+	register "pirqf_routing" = "PCH_IRQ11"
+	register "pirqg_routing" = "PCH_IRQ11"
+	register "pirqh_routing" = "PCH_IRQ11"
+
+	# configure device interrupt routing
+	register "ir00_routing" = "0x3210" # IR00, Dev31
+	register "ir01_routing" = "0x3210" # IR01, Dev30
+	register "ir02_routing" = "0x3210" # IR02, Dev29
+	register "ir03_routing" = "0x3210" # IR03, Dev28
+	register "ir04_routing" = "0x3210" # IR04, Dev27
+
+	# configure interrupt polarity control
+	register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow
+	register "ipc1" = "0x00000000" # IPC1
+	register "ipc2" = "0x00000000" # IPC2
+	register "ipc3" = "0x00000000" # IPC3
+
+	# configure MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT_CORES msrs
+	# FB production turbo_ratio_limit is 0x1f1f1f2022222325
+	register "turbo_ratio_limit" = "0x1b1b1b1d20222325"
+	# FB production turbo_ratio_limit_cores is 0x1c1812100c080402
+	register "turbo_ratio_limit_cores" = "0x1c1814100c080402"
+
+	# configure PSTATE_REQ_RATIO for MSR_IA32_PERF_CTRL
+	register "pstate_req_ratio" = "0xa"
+
+	register "coherency_support" = "0"
+	register "ats_support" = "0"
+
+	device cpu_cluster 0 on
+	  device lapic 0 on end
+	end
+
+	device domain 0 on
+		device pci 00.0 on end # Host bridge
+		device pci 04.0 on end # Intel SkyLake-E CBDMA Registers
+		device pci 04.1 on end # Intel SkyLake-E CBDMA Registers
+		device pci 04.2 on end # Intel SkyLake-E CBDMA Registers
+		device pci 04.3 on end # Intel SkyLake-E CBDMA Registers
+		device pci 04.4 on end # Intel SkyLake-E CBDMA Registers
+		device pci 04.5 on end # Intel SkyLake-E CBDMA Registers
+		device pci 04.6 on end # Intel SkyLake-E CBDMA Registers
+		device pci 04.7 on end # Intel SkyLake-E CBDMA Registers
+		device pci 05.0 on end # Intel SkyLake-E MM/Vt-d Configuration Registers
+		device pci 05.2 on end # Intel SkyLake-E RAS
+		device pci 05.4 on end # Intel SkyLake-E IOAPIC
+		device pci 08.0 on end # System peripheral: Intel SkyLake-E Ubox Registers
+		device pci 08.1 on end # Performance counters: Intel SkyLake-E Ubox Registers
+		device pci 08.2 on end # System peripheral: Intel SkyLake-E Ubox Registers
+		device pci 11.0 on end # Intel Device a26c: PCU
+
+		# PCH devices
+		device pci 11.5 on end # Intel C620 Series Chipset Family SSATA Controller [AHCI mode]
+		device pci 14.0 on end # Intel C620 Series Chipset Family USB 3.0 xHCI Controller
+
+		device pci 14.2 on end # Signal processing controller: Intel Device a231
+		device pci 16.0 on end # Communication controller: Intel Device a23a
+		device pci 16.1 on end # Communication controller: Intel Device a23b
+		device pci 16.4 on end # Communication controller: Intel Device a23e
+		device pci 1c.0 on end # PCI bridge: Intel Device a210
+		device pci 1c.4 on end # PCI bridge: Intel Device a214
+		device pci 1c.5 on end # PCI bridge: Intel Device a215
+		device pci 1d.0 on end # PCI bridge: Intel Device a218
+		device pci 1f.0 on end # ISA bridge: Intel Device a245
+		device pci 1f.1 on end # p2sb
+		device pci 1f.2 on end # Memory controller: Intel Device a221
+		device pci 1f.3 on end # Audio device: Intel Device a270
+		device pci 1f.4 on end # Intel C620 Series Chipset Family SMBus
+		device pci 1f.5 on end # Intel C620 Series Chipset Family SPI Controller
+	end
+end