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authorTimChu <Tim.Chu@quantatw.com>2020-06-02 00:02:35 -0700
committerPhilipp Deppenwiese <zaolin.daisuki@gmail.com>2020-07-16 13:07:58 +0000
commita5ca4a0c75237093f1a4d90f30c0c932e5fcd05d (patch)
treece9d9bb7b75c4b764abe2aaa44953d0810faabc4 /src/mainboard/ocp/deltalake/devicetree.cb
parentb29d16fc8a1e15a9a5e7f5b389019b7593d42d02 (diff)
downloadcoreboot-a5ca4a0c75237093f1a4d90f30c0c932e5fcd05d.tar.xz
mb/ocp/deltalake: Select IPMI OCP to send POST start/end command
Implement sending POST start/end command to BMC. TEST=Read POST command log in OpenBMC, if command received successfully, message may show as below, root@bmc-oob:~# cat /var/log/messages |grep -i "POST" 2020 May 28 13:21:22 bmc-oob. user.info fby3-v2020.20.2: ipmid: POST Start Event for Payload#1 2020 May 28 13:21:25 bmc-oob. user.info fby3-v2020.20.2: ipmid: POST End Event for Payload#1 root@bmc-oob:~# Signed-off-by: TimChu <Tim.Chu@quantatw.com> Change-Id: I38b512ee97c0eda6ba54482a448ef9ffc27b4ddb Reviewed-on: https://review.coreboot.org/c/coreboot/+/41993 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/ocp/deltalake/devicetree.cb')
-rw-r--r--src/mainboard/ocp/deltalake/devicetree.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb
index cc17e06f6c..122f4ffa2c 100644
--- a/src/mainboard/ocp/deltalake/devicetree.cb
+++ b/src/mainboard/ocp/deltalake/devicetree.cb
@@ -85,6 +85,9 @@ chip soc/intel/xeon_sp/cpx
register "bmc_i2c_address" = "0x20"
register "bmc_boot_timeout" = "60"
end
+ chip drivers/ocp/ipmi # OCP specific IPMI porting
+ device pnp ca2.1 on end
+ end
end # ISA bridge: Intel Device a245
device pci 1f.1 on end # p2sb
device pci 1f.2 on end # Memory controller: Intel Device a221