summaryrefslogtreecommitdiff
path: root/src/mainboard/ocp/deltalake
diff options
context:
space:
mode:
authorJohnny Lin <johnny_lin@wiwynn.com>2020-06-16 19:42:26 +0800
committerPhilipp Deppenwiese <zaolin.daisuki@gmail.com>2020-07-04 11:24:05 +0000
commit37f38505f279af3cb02b9ec7c70c38c1ae0005c2 (patch)
treecf37b7042fe08eda110b43f3e57407ea59d24db6 /src/mainboard/ocp/deltalake
parent5e8709f89e3e4ee385b1798730281b2a9dacdcef (diff)
downloadcoreboot-37f38505f279af3cb02b9ec7c70c38c1ae0005c2.tar.xz
mb/ocp/deltalake: Add VPD flash regions and select VPD and VPD_SMBIOS_VERSION
Tested on OCP Delta Lake. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I1e6e2bd25cbe3b0c0547dda9e457c4d55df28388 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42428 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/ocp/deltalake')
-rw-r--r--src/mainboard/ocp/deltalake/Kconfig2
-rw-r--r--src/mainboard/ocp/deltalake/board.fmd14
2 files changed, 13 insertions, 3 deletions
diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig
index 698c57b246..45fbcbf8b6 100644
--- a/src/mainboard/ocp/deltalake/Kconfig
+++ b/src/mainboard/ocp/deltalake/Kconfig
@@ -10,6 +10,8 @@ config BOARD_SPECIFIC_OPTIONS
select SUPERIO_ASPEED_AST2400
select IPMI_KCS
select OCP_DMI
+ select VPD
+ select VPD_SMBIOS_VERSION
config IPMI_KCS_REGISTER_SPACING
int
diff --git a/src/mainboard/ocp/deltalake/board.fmd b/src/mainboard/ocp/deltalake/board.fmd
index a0c8dc5f8b..847a0a6434 100644
--- a/src/mainboard/ocp/deltalake/board.fmd
+++ b/src/mainboard/ocp/deltalake/board.fmd
@@ -5,8 +5,16 @@ FLASH 64M {
PLATFORM_DATA@0x2FE8000 0x10000
}
SI_BIOS@0x3000000 0x1000000 {
- FMAP@0x0 0x800
- RW_MRC_CACHE@0x1000 0x10000
- COREBOOT(CBFS)@0x11000
+ MISC_RW@0x0 0x20000 {
+ RW_MRC_CACHE@0x0 0x10000
+ RW_VPD(PRESERVE)@0x10000 0x4000
+ }
+ WP_RO@0x20000 0xfe0000 {
+ RO_VPD(PRESERVE)@0x0 0x4000
+ RO_SECTION@0x4000 0xfdc000 {
+ FMAP@0x0 0x800
+ COREBOOT(CBFS)@0x800 0xfdb800
+ }
+ }
}
}