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| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-12-16 19:56:17 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-12-30 00:31:56 +0000 |
| commit | 6f3c5df55ba15d5df2374fbfc9aae72fa7b1a3e8 (patch) | |
| tree | d061042718648cf7e355420c4213cf43e18aae9d /src/mainboard/ocp/deltalake | |
| parent | 6c3ba50a444d969c3086ab18d5123f119295748b (diff) | |
| download | coreboot-6f3c5df55ba15d5df2374fbfc9aae72fa7b1a3e8.tar.xz | |
mb/ocp/deltalake: replace "POST complete" mb code with driver functionality
Replace the mainboard-specific code for "POST complete" signalling with
devicetree entries for using the newly introduced IPMI driver
functionality.
Test: Boot the machine via the BMC web interface and check that sensors
get read correctly by the IPMI firmware when the payload starts.
Tested successfully.
Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Change-Id: I3441c2a971cfb564b34b3a419beceb949fe295b1
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/ocp/deltalake')
| -rw-r--r-- | src/mainboard/ocp/deltalake/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/ocp/deltalake/ramstage.c | 10 |
2 files changed, 4 insertions, 10 deletions
diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb index 06448c38eb..8b6e3aea6c 100644 --- a/src/mainboard/ocp/deltalake/devicetree.cb +++ b/src/mainboard/ocp/deltalake/devicetree.cb @@ -51,6 +51,7 @@ chip soc/intel/xeon_sp/cpx end device domain 0 on + device gpio 0 alias pch_gpio on end device pci 00.0 on end # Host bridge device pci 04.0 on end # Intel SkyLake-E CBDMA Registers device pci 04.1 on end # Intel SkyLake-E CBDMA Registers @@ -86,8 +87,11 @@ chip soc/intel/xeon_sp/cpx device pci 1f.0 on chip drivers/ipmi # BMC KCS device pnp ca2.0 on end + use pch_gpio as gpio_dev register "bmc_i2c_address" = "0x20" register "bmc_boot_timeout" = "60" + register "post_complete_gpio" = "GPP_B20" + register "post_complete_invert" = "1" end chip drivers/ipmi/ocp # OCP specific IPMI porting device pnp ca2.1 on end diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 72a74daecc..afc2b69cd4 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -5,8 +5,6 @@ #include <bootstate.h> #include <drivers/ipmi/ipmi_ops.h> #include <drivers/ocp/dmi/ocp_dmi.h> -#include <gpio.h> -#include <soc/lewisburg_pch_gpio_defs.h> #include <soc/ramstage.h> #include <soc/soc_util.h> #include <stdio.h> @@ -367,11 +365,3 @@ struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, .final = mainboard_final, }; - -static void pull_post_complete_pin(void *unused) -{ - /* Pull Low post complete pin */ - gpio_output(GPP_B20, 0); -} - -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, pull_post_complete_pin, NULL); |