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authorLukasz Siudut <lsiudut@fb.com>2019-04-24 12:00:10 +0100
committerPhilipp Deppenwiese <zaolin.daisuki@gmail.com>2019-04-28 00:26:38 +0000
commite54c15aa729d2b9ae2978e1aedf4fd7bc92cf97d (patch)
tree5430d6115020f844ce44e43add3c16defd1975cc /src/mainboard/ocp/monolake/romstage.c
parente7168edeb8dead2699d0bddf98006a8e86823244 (diff)
downloadcoreboot-e54c15aa729d2b9ae2978e1aedf4fd7bc92cf97d.tar.xz
mb/ocp/monolake: add TPM and IPMI support
Changes includes: - enable TPM1 + add entry in devicetree - configure LPC IO to make IPMI work + add entry in devicetree - introduce DSDT and SMBIOS entries for IPMI to make it detectable by ipmi_si driver Signed-off-by: Lukasz Siudut <lsiudut@fb.com> Change-Id: Ia975643064075f1f861f4ead6f24ed71f345ea04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Diffstat (limited to 'src/mainboard/ocp/monolake/romstage.c')
-rw-r--r--src/mainboard/ocp/monolake/romstage.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c
index 2bb50f097b..f3ec7e32b8 100644
--- a/src/mainboard/ocp/monolake/romstage.c
+++ b/src/mainboard/ocp/monolake/romstage.c
@@ -20,6 +20,9 @@
#include <cpu/x86/msr.h>
#include <cf9_reset.h>
#include <console/console.h>
+#include <device/pci_ops.h>
+#include <soc/pci_devs.h>
+#include <soc/lpc.h>
/**
* /brief mainboard call for setup that needs to be done before fsp init
@@ -49,7 +52,9 @@ void early_mainboard_romstage_entry(void)
*/
void late_mainboard_romstage_entry(void)
{
-
+ // IPMI through BIC
+ pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN2_DEC,
+ 0x0c0ca1);
}
/**
@@ -57,5 +62,4 @@ void late_mainboard_romstage_entry(void)
*/
void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
{
-
}