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| author | Ryback Hung <ryback.hung%quantatw.com@gtempaccount.com> | 2020-04-16 19:34:03 -0700 |
|---|---|---|
| committer | Andrey Petrov <andrey.petrov@gmail.com> | 2020-05-01 16:40:11 +0000 |
| commit | f87ad9225c5dfafc266071bb4757065bca50966f (patch) | |
| tree | c6690771411cc65c4923533ddf10a86fee0fd97f /src/mainboard/ocp/sonorapass/devicetree.cb | |
| parent | d2bbc68fa32ec60f8aa83870559beadbef0d1c9f (diff) | |
| download | coreboot-f87ad9225c5dfafc266071bb4757065bca50966f.tar.xz | |
mb/ocp/sonorapass: Add Sonora Pass
Just a minimal set of board files needed to get it to boot
in 1 CPU mode.
Signed-off-by: Ryback Hung <ryback.hung%quantatw.com@gtempaccount.com>
Change-Id: Ia7b45c78b38d091bd9535899b681746e13efb4fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Diffstat (limited to 'src/mainboard/ocp/sonorapass/devicetree.cb')
| -rw-r--r-- | src/mainboard/ocp/sonorapass/devicetree.cb | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/src/mainboard/ocp/sonorapass/devicetree.cb b/src/mainboard/ocp/sonorapass/devicetree.cb new file mode 100644 index 0000000000..05dac455e3 --- /dev/null +++ b/src/mainboard/ocp/sonorapass/devicetree.cb @@ -0,0 +1,39 @@ +chip soc/intel/xeon_sp/cpx + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host bridge + device pci 04.0 on end + device pci 04.1 on end + device pci 04.2 on end + device pci 04.3 on end + device pci 04.4 on end + device pci 04.5 on end + device pci 04.6 on end + device pci 04.7 on end + device pci 05.0 on end + device pci 05.2 on end + device pci 05.4 on end + device pci 08.0 on end + device pci 08.1 on end + device pci 08.2 on end + device pci 11.0 on end + device pci 11.1 on end + device pci 11.5 on end + device pci 14.0 on end + device pci 16.0 on end + device pci 16.1 on end + device pci 16.4 on end + device pci 17.0 on end + device pci 1c.0 on end + device pci 1c.4 on end + device pci 1f.2 on end + device pci 1f.4 on end + device pci 1f.5 on end + + device pci 1f.0 on # LPC/eSPI Interface + end + + end +end |