mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH. Skylake-SP is a processor in Intel Xeon
Scalable Processor family.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Towards successful gerrit buildbot build, note that:
* microcode is in coreboot intel-microcode submodule repo.
* IFD binary is included in this patch.
* Dummy ME binary is used, as it may take long time for Intel
ME binary to be available in public domain.
* Fake FSP binary is used, as at this moment the SKX-SP
FSP binary is not going to be available in public domain.

Known issues (Not intend to address in this initial support for
Xeon-SP processors):
* c6 state is not supported.
* dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
* SMM handlers are not added.

Following are some command execution with CentOS booted from
local SATA disk:
[root@localhost ~]# lscpu
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                72
On-line CPU(s) list:   0-71
Thread(s) per core:    2
Core(s) per socket:    18
Socket(s):             2
NUMA node(s):          2
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 85
Model name:            Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz
Stepping:              4
CPU MHz:               140.415
BogoMIPS:              4626.46
Virtualization:        VT-x
L1d cache:             32K
L1i cache:             32K
L2 cache:              1024K
L3 cache:              25344K
NUMA node0 CPU(s):     0-17,36-53
NUMA node1 CPU(s):     18-35,54-71
[root@localhost ~]# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet 172.23.68.190  netmask 255.255.0.0  broadcast 172.23.255.255
        inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0  prefixlen 64 //cut
        inet6 fe80::268a:7ff:fe57:5af0  prefixlen 64  scopeid 0x20<link>
        inet6 2620:10d:c082:9063::5d2  prefixlen 128  scopeid 0x0<global>
        ether 24:8a:07:57:5a:f0  txqueuelen 1000  (Ethernet)
        RX packets 84249  bytes 6371591 (6.0 MiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 8418  bytes 748781 (731.2 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 613  bytes 63906 (62.4 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 613  bytes 63906 (62.4 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
[root@localhost ~]# cbmem
36 entries total:

// Lines were cut to avoid checkpatch.pl warnings

Total Time: 96,243,882,140,175,829

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Tested-by: johnny_lin@wiwynn.com
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>

1 files changed, 91 insertions, 0 deletions

diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb
new file mode 100644
index 0000000000..46311d9823
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/devicetree.cb
@@ -0,0 +1,91 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 - 2020 Intel Corporation.
+## Copyright (C) 2019 - 2020 Facebook Inc
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+chip soc/intel/xeon_sp
+
+	register "pirqa_routing" = "PCH_IRQ11"
+	register "pirqb_routing" = "PCH_IRQ10"
+	register "pirqc_routing" = "PCH_IRQ11"
+	register "pirqd_routing" = "PCH_IRQ11"
+	register "pirqe_routing" = "PCH_IRQ11"
+	register "pirqf_routing" = "PCH_IRQ11"
+	register "pirqg_routing" = "PCH_IRQ11"
+	register "pirqh_routing" = "PCH_IRQ11"
+
+	# configure device interrupt routing
+	register "ir00_routing" = "0x3210" # IR00, Dev31
+	register "ir01_routing" = "0x3210" # IR01, Dev30
+	register "ir02_routing" = "0x3210" # IR02, Dev29
+	register "ir03_routing" = "0x3210" # IR03, Dev28
+	register "ir04_routing" = "0x3210" # IR04, Dev27
+
+	# configure interrupt polarity control
+	register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow
+	register "ipc1" = "0x00000000" # IPC1
+	register "ipc2" = "0x00000000" # IPC2
+	register "ipc3" = "0x00000000" # IPC3
+
+	# configure MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT_CORES msrs
+	# FB production turbo_ratio_limit is 0x1f1f1f2022222325
+	register "turbo_ratio_limit" = "0x1b1b1b1d20222325"
+	# FB production turbo_ratio_limit_cores is 0x1c1812100c080402
+	register "turbo_ratio_limit_cores" = "0x1c1814100c080402"
+
+	# configure PSTATE_REQ_RATIO for MSR_IA32_PERF_CTRL
+	register "pstate_req_ratio" = "0xa"
+
+	# configure VTD
+	register "vtd_support" = "1"
+	register "coherency_support" = "1"
+	register "ats_support" = "1"
+
+	device cpu_cluster 0 on
+	  device lapic 0 on end
+	end
+
+	device domain 0 on
+		device pci 00.0 on end # Host bridge
+		device pci 04.0 on end # Intel Corporation SkyLake-E CBDMA Registers
+		device pci 04.1 on end # Intel Corporation SkyLake-E CBDMA Registers
+		device pci 04.2 on end # Intel Corporation SkyLake-E CBDMA Registers
+		device pci 04.3 on end # Intel Corporation SkyLake-E CBDMA Registers
+		device pci 04.4 on end # Intel Corporation SkyLake-E CBDMA Registers
+		device pci 04.5 on end # Intel Corporation SkyLake-E CBDMA Registers
+		device pci 04.6 on end # Intel Corporation SkyLake-E CBDMA Registers
+		device pci 04.7 on end # Intel Corporation SkyLake-E CBDMA Registers
+		device pci 05.0 on end # Intel Corporation SkyLake-E MM/Vt-d Configuration Registers
+		device pci 05.2 on end # Intel Corporation Device 2025
+		device pci 05.4 on end # Intel Corporation Device 2026
+		device pci 08.0 on end # Intel Corporation SkyLake-E Ubox Registers
+		device pci 08.1 on end # Intel Corporation SkyLake-E Ubox Registers
+		device pci 08.2 on end # Intel Corporation SkyLake-E Ubox Registers
+		device pci 11.0 on end # Intel Corporation C620 Series Chipset Family MROM 0
+		device pci 11.1 on end # Intel Corporation C620 Series Chipset Family MROM 1
+		device pci 11.5 on end # Intel Corporation C620 Series Chipset Family SSATA Controller [AHCI mode]
+		device pci 14.0 on end # Intel Corporation C620 Series Chipset Family USB 3.0 xHCI Controller
+		device pci 16.0 on end # Intel Corporation C620 Series Chipset Family MEI Controller #1
+		device pci 16.1 on end # Intel Corporation C620 Series Chipset Family MEI Controller #2
+		device pci 16.4 on end # Intel Corporation C620 Series Chipset Family MEI Controller #3
+		device pci 17.0 on end # Intel Corporation C620 Series Chipset Family SATA Controller [AHCI mode]
+		device pci 1c.0 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #1
+		device pci 1c.4 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #5
+		device pci 1f.0 on end # Intel Corporation C621 Series Chipset LPC/eSPI Controller
+		device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller
+		device pci 1f.4 on end # Intel Corporation C620 Series Chipset Family SMBus
+		device pci 1f.5 on end # Intel Corporation C620 Series Chipset Family SPI Controller
+	end
+end