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| author | Tim Chu <Tim.Chu@quantatw.com> | 2020-12-28 00:08:53 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-09 06:16:42 +0000 |
| commit | 58e1e0aee938a5a539c35ae52bfe718e41f7b224 (patch) | |
| tree | bad3cbb1ae3d07607e1c837fc4c9ec5f5ef5697c /src/mainboard/ocp | |
| parent | 5fa07217a4d3fa41fa93b7a05811584fad9dda7a (diff) | |
| download | coreboot-58e1e0aee938a5a539c35ae52bfe718e41f7b224.tar.xz | |
mb/ocp/deltalake: Override DDR frequency limit via VPD variable
Use VPD variable "fsp_dimm_freq" to select DDR frequency limit.
Tested=On OCP Delta Lake, DDR frequency limit can be changed via VPD.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I1232feae5090420d8fa42596b46f2d4dcaf9d635
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Diffstat (limited to 'src/mainboard/ocp')
| -rw-r--r-- | src/mainboard/ocp/deltalake/romstage.c | 40 | ||||
| -rw-r--r-- | src/mainboard/ocp/deltalake/vpd.h | 5 |
2 files changed, 45 insertions, 0 deletions
diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index 4272e3ad17..9227508771 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -13,6 +13,35 @@ #include "ipmi.h" #include "vpd.h" +/* Convert the vpd integer to the DDR frenquency limit enum */ +static enum ddr_freq_limit ddr_freq_limit(int num) +{ + switch (num) { + case 0: + return DDR_AUTO; + case 1: + return DDR_1333; + case 2: + return DDR_1600; + case 3: + return DDR_1866; + case 4: + return DDR_2133; + case 5: + return DDR_2400; + case 6: + return DDR_2666; + case 7: + return DDR_2933; + case 8: + return DDR_3200; + default: + printk(BIOS_WARNING, "Invalid DdrFreqLimit value from VPD: " + "%d\n", num); + return DDR_AUTO; + }; +} + /* * Search from VPD_RW first then VPD_RO for UPD config variables, * overwrites them from VPD if it's found. @@ -77,6 +106,17 @@ static void mainboard_config_upd(FSPM_UPD *mupd) printk(BIOS_DEBUG, "Setting MemRefreshWatermark %d from VPD\n", val_int); mupd->FspmConfig.UnusedUpdSpace0[0] = (uint8_t)val_int; } + + /* Select DDR Frequency Limit */ + if (vpd_get_int(FSP_DIMM_FREQ, VPD_RW_THEN_RO, (int *const) &val_int)) { + printk(BIOS_INFO, "Setting DdrFreqLimit %d from VPD\n", val_int); + mupd->FspmConfig.DdrFreqLimit = ddr_freq_limit(val_int); + } else { + printk(BIOS_WARNING, "Not able to get VPD %s, default set " + "DdrFreqLimit to %d\n", FSP_DIMM_FREQ, + FSP_DIMM_FREQ_DEFAULT); + mupd->FspmConfig.DdrFreqLimit = ddr_freq_limit(FSP_DIMM_FREQ_DEFAULT); + } } /* Update bifurcation settings according to different Configs */ diff --git a/src/mainboard/ocp/deltalake/vpd.h b/src/mainboard/ocp/deltalake/vpd.h index 55cbc5edbe..0b5a3e1d78 100644 --- a/src/mainboard/ocp/deltalake/vpd.h +++ b/src/mainboard/ocp/deltalake/vpd.h @@ -41,4 +41,9 @@ #define COREBOOT_UART_IO "coreboot_uart_io" #define COREBOOT_UART_IO_DEFAULT 1 +/* FSP dimm frequency limit, 0:Auto, 1:DDR_1333, 2:DDR_1600, 3:DDR_1866, 4:DDR_2133, + * 5:DDR_2400, 6:DDR_2666, 7:DDR_2933, 8:DDR_3200 */ +#define FSP_DIMM_FREQ "fsp_dimm_freq" +#define FSP_DIMM_FREQ_DEFAULT 0 + #endif |